Tag Archives: yield

MEMS Mirrors for LIDAR

Clever integration of new microelectronic/nanoelectronic technologies will continue to provide increased functionalities for modern products. Light Imaging, Detection, And Ranging (LIDAR) technology uses lasers to see though fog and darkness, and smaller less expensive LIDAR systems are needed for autonomous driving applications now being developed by dozens of major companies around the world. A significant step in the right direction has been taken by the US government’s Lawrence Livermore National Laboratory (LLNL) after working with AMFitzgerald on a MEMS mirror Light-field Directing Array (LDA) prototype.

In-process photo of the Light-field Directing Array (LDA) MEMS prototype designed by Lawrence Livermore National Laboratory. (Source: AMFitzgerald & Assoc.)

In-process photo of the Light-field Directing Array (LDA) MEMS prototype designed by Lawrence Livermore National Laboratory. (Source: AMFitzgerald & Assoc.)

For the past several years, AMFitzgerald has been developing the fabrication process for a novel MEMS micro-mirror array designed by Dr. Robert Panas’s research group at LLNL, as shown in this video. The technology has been developed specifically to serve LIDAR, laser communications, and other demanding applications where existing MEMS mirror array technologies are insufficient. The novel design offers exceptional speed and tilt range, with three axes (tip-tilt-piston), feedback control, and 99% fill factor. The technology is available for license from the LLNL Industrial Partnerships Office.

At the upcoming MEMS & Sensors Technical Congress, on May 11, Dr. Carolyn D. White will present a case study on how she developed this complex prototype and leveraged AMFitzgerald’s ecosystem of partners to integrate specialty processes. Dr. Alissa Fitzgerald—founder and principle of AMFitzgerald leading the development of innovative MEMS and sensor solutions for specialty applications—will be giving a keynote address on “Next Generation MEMS Manufacturing” at 9:10am May 17 during The ConFab. Dr. Fitzgerald has unparalleled expertise in how to best design MEMS for different fab lines, and is a speaker not to be missed.


Broadening Scope of SEMICON

Once upon a time, SEMICONs were essentially just for semiconductor manufacturing business and technology, and predominantly CMOS ICs. Back when we followed public roadmaps for technology to maintain the cadence of new manufacturing nodes in support of Moore’s Law, it was sufficient to focus on faster transistors connected with tighter wires. Now in an era that is at least partially “More-than-Moore”—as we like to refer to heterogeneous integration of non-CMOS technologies into commercial ICs—SEMICON West 2016 will focus on technologies beyond silicon CMOS such as MEMS and flexible organic semiconductors.

Alissa Fitzgerald, founder and managing member of AM Fitzgerald & Associates, will present on some of these themes Wednesday afternoon during the “What’s Next in MEMS and Sensors: Innovations to Drive the Next Generation of Growth” session (Track 2) of SEMICON’s Advanced Manufacturing Forum. Much of that growth is expected to be in sensors, microprocessors, ultra-low-power supplies, and communications chips to support the Internet of Things (IoT) connected by high-speed 5G data networks.

Flexible/Hybrid Electronics Forum at SEMICON West this year includes two full days of excellent presentations on new technologies that include thinned device processing, device/sensor integrated printing and packaging, and reliability testing and modeling. The following is the full list of forums this year:

  • Advanced Manufacturing,
  • Advanced Packaging,
  • Extended Supply-Chain,
  • Flexible/Hybrid Electronics,
  • Silicon Innovation,
  • Sustainable Manufacturing,
  • Test, and
  • World of IoT.

Partner programs include focused forums discussing trends in technology, markets, and the business of commercial IC fabrication. The industry’s default center of “More Moore” R&D is now imec in Belgium, and invited attendees of the imec technology forum (ITF) in San Francisco happening on July 11th the day before the start of SEMICON West will learn about the latest results in CMOS device shrinking from finFETs to nanowires. The next evening, French R&D and pilot manufacturing center CEA-Leti will lead a workshop detailing how to partner with the organization to bring sensor-based “More-than-Moore” technologies to market. Thursday morning will feature the Entegris Yield Breakfast Forum discussing the need for new materials handling solutions due to “Yield Enhancement Challenges in Today’s Memory IC Production.”

As the official event website summarizes:  We’ve deepened our reach across the full electronics manufacturing supply chain to connect you with more key players — including major industry leaders like Cisco, Samsung, Intel, Audi, Micron, and more. New players, demand generators, systems integrators, and emerging industry segments — all connecting in one place. Keynote presentations will be provided by Cisco Systems, Kateeva, and Oracle.


Omhi kept us Ultra-Clean

OhmiSadly, I just recently learned from the UCPSS 2016 website that Ohmi-sensei—Professor Doctor Tadahiro Ohmi—passed away in Sendai on 21 February 2016. As the guru of ultra-clean technology, he established the global Ultra Clean Society in 1988, founded the International Symposium of Semiconductor Manufacturing (ISSM) in 1992, served as program committee member of the UCPSS between 1992 and 2006, and was an IEEE Fellow. Ohmi was a Professor of New Industry Creation Hatchery Center at Tohoku University, after serving as a Professor at the Electronic Engineering Department, School of Engineering at Tohoku U.

Ohmi was most famous for asserting that IC manufacturing yield could be 100% if only every tool and tube in the fab were built with ultra-clean surfaces, and if all direct-materials and fluids flowing in the fab were ultra-clean. In the 1980s when IC designs and fab processes were relatively simple and HVM yields were in the 30-60% range, huge improvements came from removing “random” particles from dirty surfaces. Soon enough by the mid-1990s  “clean enough” was found to be the pragmatic response to the experience of diminishing returns after yields were in the 90% range. Most famously for posterity, in 1993 Ohmi edited “Ultraclean Technology Handbook: Ultrapure Water, Vol.1”.

I first met him when UltraClean Technology, Inc. (UCTT) was founded in California in 1996 to weld ultra-clean steel from parent company Mitsubishi in a Class-1 cleanroom, and he was the genius bringing his vision of a better world to the rest of us. However, eventually UCTT separated from Mitsubishi and added Class-100 and Class-1000 assembly areas to provide “clean enough” technology…heresy to the Guru of ultra-clean; I never met him again when I worked for the company as a product manager in 2004.

As covered by EETimes in 2002, Ohmi could clearly see that something new was going to be needed in fab technology, but his vision for a way forward was an unrealizable dream:

Ohmi said his comprehensive process, from design through chip making, would create devices with 10 times better performance than today’s chips. At the same time, he said, it would squeeze design and production time to 1/40, clean room space to 1/5 and production cost to 1/10 of what’s now required.

Throughout his career he continued to look for breakthroughs to enable new generations of semiconductor manufacturing technology, recently supervising a project to develop a “next-generation flat panel display.”

An extraordinarily prolific inventor, his name is on an astonishing 592 issued US patents, based on 795 US applications filed, the most recent on December 21st of last year.


Chasing IC Yield when Every Atom Counts

Increasing fab costs coming for inspection and metrology
ITRS2013_Yield_overviewAt SEMICON West this year in Thursday morning’s Yield Breakfast sponsored by Entegris, top executives from Qualcomm, GlobalFoundries, and Applied Materials discussed the challenges to achieving profitable fab yield for atomic-scale devices (Figure source is the ITRS 2013 Yield Chapter). Due to the sensitive nature of the topic, recording was not allowed and copies of the presentations could not be shared.
Qualcomm – Geoffrey Yu
Double-patterning will be needed for metal and via layers as we go before 90nm pitch for the next generations of ICs. Qualcomm is committed to designing IC with smaller features, but not all companies may need to do so. Fab costs keep going up for atomic-scale devices…and there are tough trade-offs that must be made, including possibly relaxing reliability requirements. “Depending on the region. If you’re in an emerging region maybe the reliability requirements won’t be as high,” said Yu. Through-Silicon Vias (TSV) will eventually be used to stack IC layers, but they add cost and will only be used when performance cannot be met with cheaper solutions. “An early idea was to use TSV for logic:memory,” reminded Yu, “but then there was innovation to LPDDR4 allowing it deliver the same bandwidth with one-half the power of LPDDR3, which delayed TSV.”
GlobalFoundries – Harry Levenson
“A more expensive part could provide a better value proposition for a customer,” reminded Levenson as he discussed the challenges of inspecting next-generation commercial ICs in high-volume manufacturing (HVM). “We still have clear demand for products to run in HVM at the leading edge, but we are now in the world of double-patterning and this applies to optical inspection as well as imaging.” Requirements for inspection and imaging are different, but he same physics applies. In imaging Depth of Focus (DoF) of ~140nm is generally preferred, while the same used for inspection  of a <140nm thin film would to induce noise from lower-levels. We can’t do e-beam inspections due to too much energy concentration needed to get acceptable throughput (and the challenge gets worse as the pixel area is reduced, inherently slowing down throughput). However, e-beams are helpful because they can detect open contracts/vias in metal levels due to the conductivity of electrons providing additional contrast compared to any possible optical inspection.
Applied Materials – Sanjiv Mittal
Mittal discussed how the CMOS transistor gate formation process has increased in complexity over the last few device generations:  8x more unit-process steps, 3x higher fab cost, 50x lower defects needed for yield. “The challenges are immense,” admitted Mittal. “What happens when you try to work on yield improvement when you’re ramping volume? At the same time you’re trying to improve yield by making changes, you’re trying to increase the volume by not making changes.”
Entegris – Jim O’Neill
O’Neill is CTO of the combined Entegris post-merger with ATMI, and was recently director of advanced process R&D for IBM. Since Entegris provides materials and sub-systems, in the simplest cases the company works to improve IC fab yield by minimizing defects. “However, the role of the materials-supplier should change,” averred O’Neill. “The industry needs bottle-to-nozzle wet chemistry solutions, and applications-based clean gas delivery.” In an exclusive interview with SST/SemiMD, O’Neill provided as example of a ‘wetted process solution’ a post-CMP-clean optimized through tuning of the brush polymer composition with the cleaning chemistry.
ITRS Difficult Challenges for Yield 2013-2020

  • Existing techniques trade-off throughput for sensitivity, but at expected defect levels, both throughput and sensitivity are necessary for statistical validity.
  • Reduction of inspection costs and increase of throughput is crucial in view of CoO.
  • Detection of line roughness due to process variation.
  • Electrical and physical failure analysis for killer defects at high capture rate, high throughput and high precision.
  • Reduction of background noise from detection units and samples to improve the sensitivity of systems.
  • Improvement of signal to noise ratio to delineate defect from process variation.
  • Where does process variation stop and defect start?