EUVL Focus


Update from EUVL Workshop in Berkeley

By Vivek Bakshi, EUV Litho, Inc.

The 2016 EUVL Workshop was held last month at LBL in Berkeley, where we heard the latest news on EUV Lithography R&D development topics. The keynote talks were given Harry Levinson (GlobalFoundries), Britt Turkot (Intel) and Igor Fomenkov (Cymer/ASML). There were progress reports on the current technical areas of focus that I will talk about below. However, I would like to point out first that since the Workshop ended, both TSMC and Samsung have announced plans to use EUV Lithography in production at the 7 to 5 nm node. Both expect to receive the NXE3400 production-level EUVL scanner during the first half of next year, which they will adapt for 7 nm node products. This speaks for itself in terms of EUVL readiness for production.

EUV source power continues to make progress, with meaningful demonstration of >200 W by both Cymer (an ASML company) and Gigaphoton. Both suppliers now think that 500 W EUV power is feasible. Not long ago, sources appeared to be the main obstacle to the introduction of EUVL into commercial production. However, presenters from Cymer (Igor Fomenkov) and Gigaphoton (Hakaru Mizoguchi) convinced me that 250 W (and hopefully 500 W) are achievable. For this reason, both Igor and Mizoguchi-san deserve to be called the “Saviors of EUVL.” Of course, they each represent a large group of multi-disciplinary teams, who have achieved a goal that many thought impossible. True, sources still need to meet operational cost and uptime goals in order to satisfy manufacturing requirements. However, steady progress is being made on this front, as pointed out by Intel in their keynote talk. I also expect 200+ W to be achieved in fabs sometime in 2017.

Although chip makers have figured out how to live with mask defects for now via defect avoidance and repairs, mask defect reduction is certainly on the wish list. Patterned mask defect inspection (PMI) is being done in different ways, with wafer inspection being one of them. Alternate PMI techniques were discussed in the presentations as well during the Workshop. Lack of a specific PMI tool remains a key issue for cost-effective, EUVL based manufacturing. I believe that lack of commercial metrology EUV sources that meet brightness requirements to support PMI and other actinic inspection tools remains a big gap, but no one seems to be coming forward and addressing this deficiency. We know we need it, so why not work on it? It is going to get more expensive without a PMI tool and other inspection tools with low throughput in the absence of a bright EUV metrology source.

Pellicles to protect masks can now withstand 125 W of thermal load, with 250 W as the present goal. I see progress, but we are not at 250 W yet.

The Industry is finally realizing that in order to make substantial progress in developing EUV resists, we need to get back to basics and better understand how they work. As EUV resists operate differently than 193 nm resists (via secondary electrons), there’s a lot that we still need to understand. There was a good set of papers on this topic, led by Frank Ogletree of LBL and others. I certainly hope that we will see lots of industry support for his work, as the return on investment on such basic research is sure to be huge.

The Workshop was moved to CXRO, LBL in Berkeley, CA this year. This year’s Workshop, the ninth to date, was the best- attended yet and offered the most papers ever. Participants found the new location very convenient with regard to travel logistics and access to area colleagues working on EUVL. CXRO continues to be a leader in EUVL R&D and has recently announced a new consortium, EUREKA, that will support continued EUVL development.

The Workshop proceedings can be downloaded at www.euvlitho.com.

Latest on EUVL Development to be Discussed in EUVL Workshop in Berkeley

By Vivek Bakshi, EUV Litho, Inc.

During this year’s SPIE Advanced Lithography conference in San Jose, there was a definite switch to optimism about EUVL from all keynote speakers. The message of “Not if, but when” for EUVL ‒ with early adoption expected in coming years ‒ was clearly heard from leading-edge chip makers and EUVL suppliers. With demonstration of 200 W source in the lab and steady progress on source power and availability, the focus has now shifted to fab productivity, mask, pellicles and resists.

This year’s 2016 EUVL Workshop is being held in Berkeley, CA, organized in cooperation with CXRO. With keynotes from Intel, GlobalFoundries and ASML, along with 45 speakers and about 50 papers, we expect to hear a good bit of new information on these topics and stimulating discussion of R&D topics. In addition, we will hear about alternate actinic inspection techniques and fundamentals of EUV resists. For EUV resist, where the chemistry is dominated by secondary electrons, researchers are looking into understanding chemical reactions in this new realm to develop resists that pattern better at EUV wavelengths.

I am looking forward to finding out the latest on EUVL in this workshop. The final agenda and abstract book is available at www.euvlitho.com

2015 Source Workshop – What we expect to hear

By Vivek Bakshi, EUV Litho, Inc.

EUV Sources remain the key enabler to move EUVL into manufacturing, and we look forward to the upcoming 2015 Source Workshop (November 9-11, 2015, Dublin, Ireland) for the latest developments and status of EUV Source technology. Both high-volume manufacturing (HVM) level and metrology EUV sources are needed for chip manufacturing using EUVL. For HVM sources, power level and availability are needed to generate cost effective throughput.

We expect to hear from the user (Intel) as well as source makers (ASML and Gigaphoton) on the latest performance of these sources. At last summer’s 2015 EUVL Workshop we learned that 80 W sources are in the field, but availability needs to improve. So we look forward to finding out the latest performance results from users and suppliers. We will also have a session of FEL-based EUV sources in this workshop. FEL is currently being explored as a technology option for 1000 W and higher EUV sources.

Metrology sources are equally important as they support mask defect metrology tools. Our agenda includes all current EUV metrology source suppliers as well as most research organizations that are working to develop these types of sources. For metrology sources, brightness, stability and source availability are the key matrix of performance.

2015 EUVL Workshop Update

I usually take a week or two to summarize the workshops that I organize or attend, as I am not a reporter but more of an analyst. However, I did not get to report on the highlights from the EUVL Workshop, as I was out on paternity leave. However, proceedings were made available after the workshop, as always.

Although much interest has been shown over the last year in the high absorbing EUV resists – which can reduce the source power requirements for HVM scanner – we learned in the 2015 EUVL Workshop that they are not ready (and may not be ready for many years to come) for commercial use. Hence, the pressure remains for source power scaling, as it will continue to be primary enabler of increased throughput in the near future.

Earlier this year, KLA-Tencor put the patterned mask defect metrology development on the back burner. We need this mask defect metrology tool for patterned wafers for manufacturing via EUVL. Hopefully, their planned merger with LAM will revitalize this program. In any case, the performance (throughput) of this and other mask defect metrology tools still depends on the metrology sources. We expect to hear about the status of these sources in the 2015 Source Workshop.

EUV Lithography – What is Next and When?

By Vivek Bakshi, EUV Litho, Inc.

This year started with an announcement, during the SPIE AL Conference, of the achievement of 100 W+ power from high volume manufacturing (HVM) EUV sources in the fab. One hundred watts at intermediate focus has been a long-standing benchmark and is a definite success, and we also can be sure that source power and availability will increase this year. The focus will now change to addressing the remaining challenges of EUVL, with questions turning on what comes next and when, as the industry prepares to deploy EUVL into HVM.

During the 2015 EUVL Workshop (June 15-19, 2015), we expect to get answers to these questions in the various keynote and invited talks. And to make sure the best information is available, we are also having a panel discussion that will address the following questions:

1. When do you expect the industry to insert EUVL into high volume manufacturing (year and process node)?

2. What are the top three challenges (technical and business) that need to be addressed to ensure readiness of EUVL for HVM? (Some examples of technical challenges are source power and availability, pellicles, mask inspection infrastructure and high absorption resists. An example of a business challenge is readiness of PMI tools.)

3. How will the industry achieve the following targets for EUV Source power: 250 W, 500 W and 1000 W?

4. When do you think that HVM worthy EUV resists with sensitivity of <5 mJ will be ready?

5. For extension of EUVL to smaller nodes, what are the pros and cons of High NA vs. Double Patterning?

6. If the industry had to start all over again to develop EUVL for HVM, what are the top three things you think should be done differently?

We hope you will join us in the Workshop as experts present their responses on these topics and answer  questions from the audience. More information on the Workshop, including the agenda and abstract book, is available on our website www.euvlitho.com.

The EUVL Workshop will be relocated from Maui to the U.S. mainland in 2016.

2015 SPIE Advanced Lithography EUVL Conference – Summary and Analysis

By Vivek Bakshi, EUV Litho, Inc.

The SPIE AL EUVL Conference was held from February 22-26, 2015 in San Jose, CA. The atmosphere in this year’s EUVL Conference was the most positive toward EUVL that I have ever seen.  Here, in this blog, I will summarize the papers and data that caught my attention, give my opinion on the latest status of EUVL, and list the challenges that are still to be addressed.

Scanner status

TSMC presented data on the latest NXE 3300B EUVL scanner. With an 80 watt EUV source, the scanner ran continuously for over 24 hours and processed more than 1000 Wafers in one day. These results are a dramatic improvement from last year, when TSMC complained about not being able to break the 10W source power barrier. Machine to machine overlay and mix and match overlay (with immersion tools) continue to improve for these scanners. TSMC also showed line and space with 15 nm half pitch and 14nm trenches. Field data from IBM for 3300B showed that optics maintains up to 90% cleanliness for six months or for 50 gigapulses. The availability of EUVL scanners is now >55% and continues to increase. ASML, in their review of status, pointed out that 3300B scanners now meet the patterning requirement for the 7nm logic node and 15nm DRAM node.

Hynix in their talk also discussed a three-day continuous run with their 3300B scanner, during which they exposed 99.85% of wafer dies on 1,670 wafers with +/- 1% dose error. This shows continued growth in the maturity of EUV scanners. Hynix claimed they can now use EUVL scanners with “sufficient productivity with better or comparable yield” compared to immersion scanners.

EUV mask Pellicle

The industry now plans to use pellicles to protect the EUV mask from defects added during manufacturing. Full size pellicles with 85% single pass transmission (30% total loss) are now manufactured by ASML and the transmission is supposed to increase to 90% this year (20% total loss). One of the impressive parts of this technology is that these pellicles can now be shipped worldwide without breakage – as I remember that damage from broken pellicles was a concern when they were first proposed. In a video demonstration, ASML showed technicians dropping a box containing the pellicles without damaging them.  Another new invention reported during the conference was that EUV pellicles can now be easily removed to allow non-actinic inspection of masks, if so desired. ASML pellicles also do not interfere with imaging as they have a negligible effect on CD uniformity (CDU) and line edge roughness (LER). Hanyang University had a paper that showed alternate material choices for EUV pellicles, which have potential for higher transmission and larger reflection of out of band (OOB) radiation.

High NA Scanner and optics

Optics quality (wave front error and flare), scanner optics throughput, and illumination schemes continue to improve and credit goes to Carl Zeiss. Numerical aperture (NA) for scanners needs to increase in order to further increase resolution – ASML has 0.5 NA on their roadmap for resolution beyond 10nm HP. Until last year, high NA options for scanners included an increase of mask size to 9” and/or a decrease in throughput. None of these options seemed to be agreeable to all parties (mask makers or chip makers). However, since then a new design called “anamorphic optics” has been proposed by ASML and Zeiss. This will have 8x magnification in the scan direction and 4x magnification in the other direction, as normalized image log slope (NILS), with a target of 2, needs to improve for horizontal lines only. There were several papers on anamorphic optics – mask design to simulation of optical performance. As this option will pattern only half field, ASML had proposed solutions to compensate for throughput loss: increase in speed  of reticle stage, deployment of central obscuration in the illuminator and increase in the average reflectivity of mirrors (via narrowing the angles in the optics).  It was also pointed out in a paper that 4x by 8x  magnification at half field offers a process window similar to what we can get from straight 8x quarter field magnification. Based on this data, it looks to me like this new optics design will be adopted by the industry for high NA EUVL scanners. (I only wish the increase in throughput options via greater stage speed and improved optics had been adopted earlier to give a boost to the throughput of current 0.33 NA tools!) It was also mentioned that high NA tools will allow scaling to two additional nodes beyond 10nm resolution, instead of needing to move to multiple patterning.

EUV Source

The best paper of the conference (in my opinion) was from Alexander Schafgans of Cymer, as he explained in detail information about the performance of shipped, in-development and planned EUV sources from Cymer. This was new information not shared publically before. The extinction of pedestal in CO2 laser pulse was the main reason for the increase in the power from 30 to 80W. Today, Cymer has an in-house 100 W source which operates with 3.5 % conversion efficiency (CE), 15 kW drive laser and 17% overhead cost (meaning only 87% of the light output is used to ensure required dose control). With a master oscillatory power amplifier (MOPA) and pre-pulse based system, they eventually hope to get 5.5 % CE with a 27 kW CO2 drive laser. If there is no additional factor that lowers the performance of source, this proposed switch should give them a factor of 2.6 over current source power or ~ target of 250W. However, based on current field data, I expect only 125 W to be reliably available in field this year. I am not quite ready to support prospects of reliable 250W by the end of this year, although this power level now seems to be feasible in the near future.

Gigaphoton, the other high power source maker, issued a press release before the symposium announcing 142W at 50% duty cycle (71 W average power). This source operated at 4.2 % CE and 70 KHZ in a burst mode for a short time. In December of last year, they also achieved 120 W at 50 % duty cycle for 2 hours. They now have ~15 days availability of debris mitigation scheme and their approach is to obtain 250W in burst mode first and then work on improving the source availability.

Free Electron Laser (FEL) based EUV Sources

I did not see any plans from LPP based source suppliers (Cymer and Gigaphoton) to scale the power beyond 500W range, and now the industry is increasingly focusing on FEL based EUV sources for higher power options of 500- 1000W, which will be needed for high NA scanners.  Erik Hosler of GlobalFoundries gave an overview of various technical options for developing an FEL prototype. I would like to see more papers and discussions on this topic, and so I am organizing a special session on FEL based sources in the upcoming 2015 EUVL workshop.

EUV Resists

The most important news about EUV resists came from a side meeting during the conference that I could not attend. Due to strict outgassing requirements, put in place to protect the scanner optics, it takes a long lead time to get a new EUV resist approved to be evaluated in the EUVL scanner. These outgassing testing requirements are now gone for chemically amplified resists (CAR), as most EUV CAR have been passing the requirements and hence the outgassing test is not critical. For other non-CAR chemistries, up to 100 wafers can be processed in the EUVL scanner before needing outgas testing certificate to continue. This change in requirements ought to drastically increase the number of new chemistries that are being tested for performance, speeding up EUV resist development. In any case, I will assume that outgassing tests will still take place for the few selected CAR candidates for high volume production and for promising new non-CAR chemistries. I would also like to point that there is now lot more focus on negative-tone CAR resists for EUV for meeting the resist requirements.

Intel had a nice paper giving the status of high absorbing EUV resists based on metal oxides, when used in a production environment. The current commercial HfO2 based resist show a shelf life of three to four weeks only, which needs to improve. The patterning performance of these results needs to progress as well, as these resists also have an issue with contrast, and demonstrated scumming and pattern collapse. Intel is currently working on a dry develop process to improve the performance of these resists.

I had been waiting to hear about these metal oxide based EUV resists, as due to high absorption property, they can dramatically reduce EUV dose requirements and hence relax source power requirements. However, it looks like they are not quite ready for production and some people pointed out to me during the conference that it can take three to five years to get a resist ready for high volume production. In a later paper in the same session, Chris Ober of Cornell University showed data on high sensitivity HfO2 (2.2 mJ) and ZrO2 (1.8 mJ) resists, but both resists had LER of ~ 6nm. In an EIDEC paper, I also noted 1.5 mJ resists but LER appeared to be high, although numbers were not given. Chris Ober also pointed out that the nano-aspect of these metal resists does not make it more toxic and these resists have passed outgassing tests at IMEC. Commenting on the Intel paper, presented by one of his ex‑students, he thinks he has some ideas to address the shelf life issue. I also hope that LER requirements will be met, as they are critical for acceptance of a resist for production.

EUV Masks

Although mask defectivity continues to drop, as shown for Hoya mask blanks by TSMC, more work is needed to reach acceptable mask blank defect levels. Patrick Kearney of SEMATECH presented a paper on the use of magnetron, instead of current ion-beam deposition (IBD) technology, to produce mask blanks. The magnetron technology, although still behind IBD in terms of defectivity, provides better reflectivity and better manufacturability. Also, mask pattern shift is the method that is increasingly being employed to reduce defects in patterned masks.

Obert Wood of GlobalFoundries presented a paper on alternate multilayer materials for masks to support higher NA scanners (Ru/Si multilayer with carbon interlayer instead of Mo/Si), which will allow less shadowing and hence smaller through-focus pattern placement errors. The topic of alternate materials for masks was again brought up in the mask topography session in papers from EPFL (Switzerland) and TSMC, showing improved imaging results via using alternate buffer layer materials.

Pei-Yang Yan of Intel talked about her work on reducing the contribution of mask-related LER to the final images. She is now able to get mask roughness down to 47 pm, which contributes only 0.3 to 0.7nm LER to images.

Mask Defect Inspection

Carl Zeiss plans to deliver an AIMS tool in Q4 of 2015 to support mask defect repair, and chip makers are discovering alternate ways to find defects on patterned mask, while an actinic patterned mask defect inspection tool is not available. However, I was happy to hear that KLA-Tencor will have a paper in the upcoming 2015 EUVL Workshop on the status of their actinic inspection tool – as actinic inspection is needed for the shift to high volume manufacturing. Despite a rumor that a high throughput e-beam inspection tool will be presented in the conference, which when combined with a removal EUV mask pellicle would eliminate the need for actinic inspection of patterned EUV masks, I did not hear of such an announcement. So if I missed this news, maybe someone can update me. Even with a pellicle, EUV patterned masks may still have defects that are generated during production from handling, or from contamination trapped between masks and pellicles. Although existence and frequency of these defects has still not been proven, chip makers will prefer to have a through pellicle actinic inspection for patterned EUV masks.

There was also a very nice presentation from Ken Goldberg of LBNL, giving an overview of the SHARP microscope, a tool being used by chip makers to actinically review EUV mask defects. Such projects highlight the value of technology and the skill set available at national labs to support the development of EUVL.

So When EUVL Will Reach HVM?

I had a lunch with a business analyst, who viewed EUVL and this whole debate on NGL as one of the greatest technical challenges of our time. I agree. To him and some readers of my blog, the key question is when will EUVL be used in high-volume production. Per the ASML roadmap, the throughput of NXE3350 at 125 W is ~ 75 Wafers per hour (WPH), and with two 3300Bs being upgraded to 3350 levels and two new 3350 scanners operational at TSMC this year, TSMC can hope for throughput  ~ 300 WPH later this year from their four NXE3350 EUVL scanners.  As source power climbs to 250W in these scanners, throughput per scanner will climb to 125 WPH, or 500 WPH for four scanners. These throughput numbers indicate the capability for moving beyond mere product development. Unfortunately, we will know that EUVL is coming to HVM for sure only when it is announced by one of the leading edge chip makers – GlobalFoundries, Hynix, Intel, Samsung, Toshiba, or TSMC. I am expecting to hear such news in 2016 or at the latest 2017, when topics such as source availability, resist readiness and actinic inspection have been addressed.

Zen and the Art of Technology Development

This winter my favorite Zen teacher is teaching a course on the topic of “Faces of Compassion – Vows of Bodhisattvas.” I learned that Bodhisattvas (beings spiritually advanced but not yet enlightened) reflect the deepest part of ourselves. When we are working in our daily lives (developing new technology which may be a better EUV source or something else) we are living our “vows” and that is how we serve others and ultimately ourselves. I mention this as I see similarities between the fundamentals of technical development and the principles of vows of Bodhisattvas. Computer chips and their manifestations as iPhones or laptops or routers or servers are driving the leading edge of what we humans do today in war or in peace, and what we do is embodied in the “vows” we undertake to serve. Our introspection combined with a global view will reveal the way forward.

Quoting Zen teacher John Tarrant:

“The journey of Buddha isn’t a literal journey that happened long ago… It is here now and paying attention helps you notice that. If you look into the life you have, your looking will lead you into a new life. What you meet on the way is part of the way.”

(John Tarrant, Sudden Awakening)

As philosopher Joseph Campbell once said, “Myths are public dreams and dreams are private myths,” and Moore’s Law is the myth that we chip makers and suppliers are publically living, hoping for EUVL as its enabler.  I and many others have dreamed that EUVL will happen and finally we are seeing the light (so to speak). Now we need to look at what worked and what did not, and why. What are the root causes of the problems we encountered, and how do we address them moving forward?

I have continued to promote EUVL as I have found this technology to be the right and elegant way to move forward. True solutions are often elegant and demonstrate “Satyam, Shivam, Sundaram,” a famous Sanskrit saying which can be translated in various ways but which more or less means that existence itself is enlightened and has been all along. These have been tough times and results are now speaking for themselves. I leave you with this quote from Mary Oliver:

Maybe the desire to make something beautiful

Is the piece of God that is inside each of us.

…….

If being so beautiful isn’t enough, what

Could they (blue horses) possibly say?

(Mary Oliver, Franz Marc’s Blue Horses, Penguin Press)

EUVL – Remaining challenges and preview of topics for the 2015 SPIE EUVL Conference

By Vivek Bakshi, EUV Litho, Inc.

With the 2015 SPIE Advanced Lithography (AL) conference around the corner, some people have asked me what remaining EUVL challenges need to be addressed to ensure it will be ready for mass production later this year or next.  Here are my thoughts on this topic and what I expect to hear at the conference.

The short answer is that we need to see a continued increase in reliable EUV source power in field and address the lack of readiness of EUV mask infrastructure in order for EUVL to be production-worthy in 2016. We expect to hear a lot on these two topics at the SPIE conference. The long-awaited breakthrough in source power was announced in summer 2014 (link). The availability of 50 W source on a long-term basis in the field was a major announcement and morale booster for the EUVL community. Since then, we have seen data for 80 W sources in labs (Link 1 Link 2 Link 3 ). I expect to hear that 100 W sources are now available in labs and I expect reliable 100 W+ in field in 2015. Many now believe that FEL-based EUV sources will drive power beyond 250- 500 W. Although there will be one paper on this topic in the SPIE meeting, one can look elsewhere for additional coverage on this topic (link).

Delay in the readiness of EUV Mask infrastructure is now the focus of chipmakers. Although Mask defect density has come way down (thanks to SEMATECH’s efforts over many years), it still needs to improve to meet manufacturing requirements. As there is only a single supplier of mask blank deposition tools, the most progress in defect reduction may come from mask repairs and by avoiding the addition of defects during manufacturing with the help of pellicles and mask cleans. Lack of readiness of actinic mask inspection tools remains a big gap, so let us see what progress we hear on this topic at the conference.

At last year’s SPIE AL meeting, there were many announcements for high absorbing EUV resists –with the implied promise of reduction in source power requirements (link). However, I did not see them making way into the EUV product development lines, as most of the development results last year were still with resists with sensitivity of  20 mJ or higher. I look forward to seeing if any of the high absorbing EUV resists proved to be production worthy.

This year started for me with the analysis of what has worked and what has not for EUVL. Lack of readiness of metrology sources is the key reason for the delay in readiness of actinic mask defect inspection tools, and the lack of support for the development of metrology sources by research consortia has not helped. There are several metrology source suppliers – Adlyte, Energetiq, Ushio and Zplasma, plus many others – who have come and gone or are standing on the sidelines. Even a small portion of a consortium budget to engage and encourage these metrology source suppliers would be a very welcome and wise move that would result in readiness of the critical element of mask defect inspection tools. The industry’s present position that metrology source suppliers must engage directly with inspection tool makers, has not worked well.  Inspection tool makers are keeping a position that they will buy a metrology source when it is ready, but metrology source suppliers lack the resources to launch major efforts to produce high brightness sources on their own. Hopefully, this year someone will point out that the delay in readiness is a consequence of the industry’s decisions and they are fully capable of addressing this issue, by strengthening this weak link.

I believe that in the near term, EUVL extension will come via multiple patterning and not via high NA options (which comes combined with a need to go to larger 9“masks) and the 6.x nm option now has been largely put on the back burner. I will report back here in this blog what I hear at the SPIE AL conference. And yes, if you have been wanting to ask detailed questions about EUVL, you are welcome to take the EUVL short course that I will be teaching with my colleagues Patrick Naulleau (LBNL) and Jinho Ahn (Hanyang University) at this conference (Link) and then again during the EUVL Workshop in June (link).

2014 EUV Source Workshop Summary

By Vivek Bakshi, EUV Litho, Inc.

Short Summary

At the 2014 Source Workshop in Dublin, the semiconductor industry’s largest annual gathering of EUV source experts, we received the latest updates on current EUV source technology (Sn laser-produced plasma [LPP]) and discussed potential and challenges of Free Electron Laser (FEL) based sources as the next generation high power EUV sources.

The most meaningful data on the performance of the sources is from the field at chipmakers, and that is what we received in the Workshop. Currently three EUVL scanners have sources with power of > 40 W and one with >80 W on a long-term basis. I believe that road is headed toward >100 W of sustained power in the field in 2015 and continued growth of EUV source power. FEL is now seriously viewed as the potential technology for EUV source with >1000 W power, and we had two sessions on the topics of FEL and FEL optics to explore technical and business challenges.

Keynote talks

The first keynote talk was from Mark Philips of Intel. Last year in the Source Workshop he declared that “source power roadmap has lost credibility” and this year he reported that “source power roadmap is regaining credibility.” He said that there are now four sources for NXE3300B operating at customer sites with > 40 W of power. One source is operating at a customer site for > 80 W (corresponding to ~ 55 WPH and 20 mJ/cm2 dose).  Mark also pointed out that the cost per wafer of the lithography step with EUVL is dependent on source power, source availability and its operating expense (mostly collector), and these numbers still need to be firmed up. His overall message on EUVL was positive, with clear guidance on focus areas to ensure EUVL is ready for high volume. His presentation can be downloaded here (Link).

Wim Zander of ASML in his talk (Link) confirmed the source data from Intel and added that IBM’s source (Link) has been operating at > 40 W for over two months (news of which caused a stir earlier this summer) and > 80 W data from a chip maker is for over 24 hours of operation. The source collector life time has now improved to over 20 weeks (40 G pulses) and the main issue for availability of sources of <40% is the droplet generator.

The second keynote talk was given by Hakaru Mizoguchi of Gigaphoton (GP) (Link). ASML acquired Cymer last year – so GP is the second supplier of high power sources for EUV scanners. He reported 42 W, 50% duty cycle or 21 W average for 3 Hours (110 M pulses). For higher power at 60 K Hz, 70% duty cycle, 10 minutes  operation to demonstrate 83 W average power (or 118 W peak power) for a total of 20K pulses, 3.7 % conversion efficiency (CE) using a 10.2 kW CO2 laser. This is solid progress and in response to an audience question, he mentioned 2017 as the date when he expects his EUV sources in the field.

All this adds up to good news for EUVL in terms of supporting product development, which I believe is continuing in earnest at four leading chip maker sites.

Focus of the challenge for EUVL now is moving to infrastructure development, which now lags behind source and scanner readiness. However, I will caution that availability of high power sources needs to remain the #1 challenge – as chip makers are asking for 250 W for production requirements and we are not there yet! The leading EUVL infrastructure topic, per Mark Phillips, is the actinic metrology source; as with the presence of pellicle, actinic inspection will be required. The availability of actinic metrology sources and commercial pellicles seems to be the next challenge and the clear requirements for metrology were presented by KLA-Tencor, Zeiss and Lasertech for metrology sources. Adlyte and Energetiq presented the status of their metrology sources to support the actinic inspection tools. I am hoping that the industry will treat the lack of suitable metrology sources as urgent, because engagement with and the support of metrology source suppliers will need to increase.

FEL Update

FEL based EUV sources are being considered as candidates for > 1000 W EUV sources, and several SASE (self-amplified spontaneous emission) FEL proposals for readiness in 5-7 years were presented. In two sessions, several papers outlined the challenges for FEL and potential solutions. Papers from Uchiyama (Toshiba), Yurkov (DESY), Murokh (RadiaBeam), Endo (Waseda) and others outlined overall FEL challenges. Sobierajski (Polish Academy of Sciences) outlined the challenge of optics damage in FEL. The desired high power may be obtained via scaling to MHz operation and currently identified challenges are – temporal spikes (need for seeding – proven in concept by FERMI group), efficient energy recovery LINAC (ERL), need for a large amount of super conductive magnets, challenge of resist sensitivity vs. ablation threshold, optics damage, coherence and radiation from circulating high energy electron beams and in beam dumps.  The proof of concept from working prototypes, cost, and time for readiness also remain challenges for realization of FEL-based high power EUV sources.

The proposal from Eiji Kako of High Energy Accelerator Research Organization in Japan stood out as a very thorough plan for FEL prototype development, and I will support their proposal to build FEL prototype tools over next five years. We have many questions and challenges to address for FEL and we will learn more from a working machine.

Highlights and Other Impressive development results 

Nishamura of Osaka University showed that there is a correlation between laser absorption and conversion efficiency (CE) of sources. His models have predicted that 6-8 % CE can be achieved. According to him, the lack of number of radiators, at high CE modes, can be compensated by increasing the droplet frequency.

In several modeling papers, generation of mist targets from the irradiation of Sn droplets from the laser pre-pulse was discussed. The physics of mist generation is still not fully understood and I also think that integrated models of Sn LPP plasma are very much needed as well.

Intel showed that up to 10 mask defects now can be covered by shifting the patterns in 2D.

~50 nm thick free-standing membranes, to be used as pellicles for EUV masks, are now routinely shipped around the world undamaged via ordinary shipping. This is no less than magic – if you have been following the pellicle development saga.

Other news and summary

The Source Workshop for some time has been expanding to other topics of interest for the Source R&D community. This year’s focus was on water window microscopy, with a keynote from Prof. Carolyn Larabell of UC San Francisco (Link), which was very well received by the audience.

The number of registered Workshop attendees and the number of papers grew this year by over 30%, indicating growing interest in EUV and XUV sources, which may be due to recent good news on source performance. Based on the EUV source performance improvement that I have seen, we can expect 100+ W sources operating the in the field in 2015. It may not seem much to some skeptics –but for people like myself, 100 W of source power has been a holy grail and I am very delighted to see that goal possibly within reach by SPIE AL in late February 2015. I support Kako-san’s detailed plan to develop the industry’s first prototype for 13.5 nm FEL based EUV source, and I believe it is important to have a working prototype – while the industry discusses all the FEL challenges and best way to solve them. The 2014 Source Workshop proceedings can be downloaded at this link.

Thoughts on the Significance of IBM’s EUV Benchmark

By Vivek Bakshi, EUV Litho, Inc.

Since I posted in last week’s EUVL Focus blog the news of IBM’s EUV benchmark with the NXE3300B scanner at the EUV Center of Excellence in Albany, this news has received lots of attention, as it is a significant achievement. I have also received some questions and comments. I believe most of them come from a lack of familiarity with leading edge tool development and with EUV Lithography itself, which is a rather narrow area of specialization.  As I tend to give long answers and reviews (because I believe details are important) in this blog I will give first give a “short-short answer” followed by a “short answer.” I will leave the “long answer” regarding the significance of this announcement for future blogs.

Short-short answer:

There is no change in the significance of what was reported last week. ASML and IBM reconfirmed the benchmarking in press and via social media. In short, 637 wafers per day throughput stands, resulting from the successful upgrade of source power by 100%, to its targeted level of ~43 W. Of course, this is a data point that needs to be confirmed over a longer period and by additional leading edge chip makers, but this was already suggested from the very beginning.

Short Answer:

(1) In the process of benchmarking leading edge tools, the performance of the tool is divided into several sections and each part is validated separately. One can divide an EUVL scanner into the major components of optics, source, mask and resist. All parts, except higher power for EUV light source, have been validated for a long time – with challenges remaining but no showstopper. High source power has remained the #1 issue and a potential showstopper. The ~40 W EUV light sources were deployed but have been working at the lower level of 20 W. The validation at 43 W is a ~100% improvement in source power. The previously reported throughput for an EUVL scanner was 200 wafers per day (WPD), so 637 WPD is over three times improvement and exceeds ASML’ s own expectation of 500 WPD for 2014. One chip maker earlier this year privately told me that ~1000 Wafers per day is acceptable for the selection of EUVL for high volume manufacturing (HVM). Hence, this excitement can be understood. I believe that ASML has moved to WPD as the new unit for the measurement of performance of their EUVL scanner, as this is more meaningful unit to chipmakers than source power, as it directly relates to productivity.

(2) The imaging performance of EUV scanners (CD, CDU, pitch, LER) are a function of scanner design, optics, mask, source and resist. The performance of these parts, except source, has been confirmed for some time now and needs no new validation. The source stability has some effect as well on imaging; hence, the power has to be stable and it is one reason for lower power results from the field. However, the #1 issue for EUV has been the throughput of the EUV scanner, which is directly related to the power of the source, as I mentioned above. Although one will eventually test the imaging performance at higher power levels, it does not make sense to be doing that imaging test (and when you know that part works fine) when you are testing for source power upgrade verification – your main challenge. This is how one benchmarks complex machines. As IBM pointed out, it was an unintended but very exciting result of their benchmark, as the focus was to validate higher source power. Other parts of the scanner and the overall imaging performance have been verified by several chip makers for some time.

(3) The next version of the NXE3300B EUV scanner will be potentially used for patterning at the 7 nm and 5 nm nodes. The resolution of printed images will be increased by either multiple patterning (EUV MP), which has been already demonstrated, or via high NA optics (projects are in progress but no demonstration of a high NA EUV tool has occurred yet). Please see the keynote talks from Toshiba and Intel in the 2014 EUVL Workshop proceedings at www.euvlitho.com to get additional information on these topics.

(4) 20 mJ of dose for a chemically amplified (CAR) resist, to test the throughput of a EUV scanner, is a very decent dose choice and it is backed by ample data. If this benchmark was done for a 5 mJ CAR resist dose, I will question the test as well, as final images will not meet LER requirements. The good news is that due to recent developments in the high sensitivity resists, now 2-5 mJ dose can give us the same resolution and LER, as from 20 mJ or higher dose CAR resists.  In the 2014 SPIE AL meeting, there were many papers confirming the performance of these new types of resists. Hence, the triangle of death (sensitivity, LER and resolution) for CAR resists is no longer valid for these new types of resists. The implications of these new resists are very striking – if we can use these new 5 mJ resists – the throughput will be 3-4 x larger than what is reported for 20 mJ resists. I am hoping that these new high sensitivity resists will mature in another year for HVM use.

(5) Some comments in the press have made over the years, hinting that a “leading chip maker” is working on 193 nm multiple mattering (193 MP), the current workhorse, in addition to EUV for the next node of patterning technology. The comments are made as if this is a “negative” implication for EUV. The fact is that every leading chip maker has been looking at both technologies (193 MP and EUV plus EUV MP) for a long time, and will continue to do so until EUV is in production to hedge their risks, and expecting anything else would not be wise. 193 MP extension is costly due to tooling and mask costs, low throughput of overall manufacturing line and lower yields. This choice also puts severe restrictions on what can be printed. EUV relaxes k1 value by turning the wavelength knob in the Rayleigh’s resolution criterion and hence the emphasis on EUV.

(6) I will not try to pretend that I understand how the stock market works, but the stock of ASML did jump over 14% in one day with this news of new EUV Benchmark. What some people do not know is that ASML is a winner if the industry chooses EUV/ EUV MP or its competitor of 193 MP. ASML is the only maker of EUVL scanners and the leading maker of scanners used for 193 MP. It is a win-win situation for ASML either way, and few other high tech companies can claim such a strategic advantage.

I hope this explains the significance of the EUV benchmark news. In the longer version of my response, I will explain different sections of the EUV scanner and how and why the throughput of the EUV scanner is related to NA, mask, resist, optics and source performance. In addition to writing this blog, organizing EUV related workshops and consulting work, I also teach, together with two of my colleagues, a short course on EUV Lithography twice a year (during the annual SPIE AL meeting and during the annual EUVL workshop).I also hope that if this topic is of interest, I will see you in the classroom where we all can have further discussions.

New Benchmark Established for EUV

I received this news from Dan Corliss of IBM today and it is reproduced below. Dan is the EUV Development Program Manager for IBM. As the previous goal for ASML scanner for 2014 was 500 wafers a day, this is definitely big news. Dan called it a “watershed moment” in his LinkedIn post. Of course, we need to see this type of performance to happen longer term like weekly basis, and it needs to be repeated by several leading edge chip makers but this is a sign of good things to come. Congratulations to Dan and his team, ASML and Cymer for significant achievement. We needed this and it looks like this EUVL is finally getting ready for production!

IBM’s NXE3300B scanner, at the EUV Center of Excellence in Albany, recently completed a “40W” EUV light source upgrade.  The upgrade resulted in better than projected performance with 44W of EUV light being measured at intermediate focus and confirmed in resist at the wafer level.  In the first 24 hours of operation after the upgrade  637 wafer exposures were completed in normal production lot mode with:

– 20 mJ dose

– 83 image fields/wafer (full wafer coverage, including partial die)

– conventional illumination

This is a watershed moment for EUV as it establishes the benchmark capability of the EUV source and scanner to support semiconductor technology node development.

EUVL pic

2014 EUVL Workshop: Highlights and Summary

By Vivek Bakshi, EUV Litho, Inc.

Keynote talks

The 2014 EUVL Workshop was held late last month amid some positive highlights and lots of R&D updates. The keynote talks this year were from Intel, Gigaphoton and Toshiba.

Intel in their keynote, paraphrasing Mark Twain and Mark Bohr, said that “rumors of scaling’s death are greatly exaggerated!” I tend to agree. In terms of choices for upcoming technology nodes, Intel is doing 14nm with 193nm lithography, and for 10nm, there is an EUV pilot line in addition to the primary approach of 193i extension. Overall, Intel will insert EUV when production tools are available and affordable, which depends mostly on EUV source readiness.

In the next keynote, Gigaphoton shared their latest results of 62 W at intermediate focus (the location where power is measured for forecasting the productivity of an EUVL scanner). This was achieved via 3.9% conversion efficiency (CE) at 50 K Hz for a low duty cycle of 5%. Mizoguchi-san from Gigaphoton expected that in coming weeks via doubling the frequency, he might be able to double the source power to >100 W. After the workshop, Gigaphoton put out a press release on July 1, reporting 92 W source power with 4.3% CE. We look forward to an increased duty cycle, an increase in operation frequency to 100 K HZ, and shipment and performance at a customer site, which they said was planned for 2015.

Toshiba’s speaker, Uchiyama-san, in his keynote talk outlined interesting solutions for the extension of EUV. A high NA option, in addition to double patterning, has been outlined by the industry to allow EUVL to continue to shrink patterning beyond 7 nm. However, the high NA scanner option has been debated without a decision due to consequences for mask size and throughput. Uchiyama-san of Toshiba pointed out an option of etched mask for high NA, which will allow the use of the current mask size and throughput, hence bypassing difficult choices. To support his proposal, he showed results for etched multi-layer masks.

Highlights

Cymer in their invited talk noted that NXE3100 (previous versions of ASML EUVL scanners) sources now have >70% availability with 70G pulses average lifetime, while >100G pulses are needed for HVM. Their sources for NXE3300B are now in the field and are being integrated. These sources in lab use demonstrated ~ 40 W with 2.5 % CE, 35% dose margin and a collector lifetime for >5 G pulses.  For standalone next version of lab sources, they are now at 75 W in open loop power and 70 W in stabilized mode.

Toshiba proposed free-electron laser (FEL) as a candidate for > 250 W EUV sources. They had feedback from FEL experts that FEL sources can be made even cheaper than LPP based sources. I expect to hear more details from Toshiba and other FEL experts on their proposed designs for FEL for 13.5 nm as well as the details on the cost of ownership.

R&D Progress Notes

The Workshop, with its focus on R&D topics, had quite a few good papers with encouraging reports of progress.

  • HiLASE is developing Nd: YAG lasers for pre-pulse technology to support HVM EUV sources. One of their project goal is to have lasers with 3.3 mJ pulses operating at 150 K Hz with 500 W average power and <10 ps pulse width. After starting with their project over a year ago, they now have lasers with 0.8 mJ pulse energy,  average power of 85 W 100 K Hz, with pulse width of <2 ps.
  • Efficient CO2 lasers are important for power  scaling and Koji Yasui of Mitsubishi Electric Corporation described their transverse gas flow CO2 lasers that they are developing to support Gigaphoton’ s EUV sources. These lasers have higher amplifier gain (meaning higher power), lower gas flow speed and short length to achieve stable operation (resulting in a smaller foot print), as compared to axial flow CO2 lasers. Their lasers provide 1.6 x times more power than axial-flow CO2 for the same input of 400 kW. Currently they have an output power of 21 kW (33% duty cycle); four amplifiers driven by two-line oscillator give an output pulse of 23 ns.
  • Power scaling of HVM sources also results in more tin debris, and in-situ cleaning is one of the many methods to remove the residual tin from collector surfaces. David N. Ruzic of UIUC showed his plasma based cleaning method that results in a very small reflectivity loss (1.2%) when cap layers of collector mirrors are exposed to plasma cleaning.
  • Speakers from Korea, China, Taiwan, Europe, Japan and USA presented an overview of EUVL related regional activities in their respected regions, indicating an impressive set of investments, but also outlined lack of funding for research on EUV sources.
  • Yanqiu Li and Zhen Cao of Beijing Institute of Technology presented their design of EUV objective with a co-axial objective systems of 6 mirrors (NA 0.5), 8 mirrors (NA 0.4) and 10 mirrors (NA 0.75), and an off-axis objective system of 6 mirrors (NA 0.4). They also presented a design of an EUV scanner illuminator system with illumination uniformity better than 2.5%.
  • Hiroo Kinoshita of University of Hyogo presented data on the performance of his new reflectometer. This is the largest reflectometer in the world and can measure up to 800 mm optics.
  • Yuriy Platonov of Rigaku Innovative Technologies presented data on the performance of his In-line Gen 2 system multi-layer deposition system. The system can now make depositions of up to 750 mm optics and is capable of velocity profiling for illuminator optics. This deposition system has a high throughput to support high volume production. He also has shared performance information on his new EUVL optics refurbishment facility, which can perform etch and clean operations.
  • Actinic inspection will be needed for EUVL HVM and new techniques and instrumentation are being developed. Kuen-Yu Tsai of  National Taiwan University presented a non-imaging defect inspection method with non-imaging optics hardware. His actinic inspection method estimates the size of defect features from scattering signal.
  • Rupert Perera of EUV Tech presented data on his 4th generation Reflectometer. This new version of the tool can measure reflectivity from a 5-10 degree angle with a spot size of 1.8 mm x 1.8 mm2 and 3 sigma of 0.3 %.
  • Jung Sik Kim of Hanyang University presented his design of thin attenuated phase shift mask (PSM) that helps reduce effect of photon shot noise. The modeling suggests that proposed mask design will result in improvements in image contrast, image log slope (ILS), CD uniformity (CDU), contact edge roughness (CER) and dose to size.
  • Sushil Padiyar of Applied Materials outlined progress in EUV mask clean and etch. Using wet and dry cleaning methods, he estimated that there was only 0.018% reflectivity loss per clean and for 50 cleans, measured 0.02 nm increase in Ru surface roughness. These measurements were done for Ru Cap mask blanks. For pattered masks, there was <0.05 nm clean CD loss per cleans. For EUV patterned mask etch, his company has demonstrated <2 nm 3 sigma EUV mask etch CDU and considers their tool to be ready for EUV HVM.
  • Hiroo Kinoshita, University of Hyogo, presented the latest results from his Coherent EUV Scattering Microscope (CSM). Now phase defects of 25.5 nm width with 1.4 nm height can be detected by his tool.
  • Takahiro Kozawa of Osaka University, describing studies of Stochastic Effects in Chemically Amplified Resists, gave a summary of design of materials for 16 and 11 nm nodes. He also identified the parameters that are needed for characterization of the potential materials for EUV resists.
  • Patrick Naulleau of LBNL, in his paper on impact of EUV mask roughness on inspection, noted that the roughness has significant impact on inspection and the scatterometry measures true EUV roughness. He also believes that actinic characterization is likely required for EUVL in HVM and that the system modeling points to EUV roughness requirements close to 50 pm.
  • Yoshi Hishiro of JSR Micro described his projects for the development of novel EUV resist materials for the reduction of EUV resist defects. He pointed out that High Tg resin improves resolution and LWR, and that the profile control is important for resolution. He presented results showing that defectivity improvement is possible by controlling resist hydrophobicity.
  • The role of secondary electrons in EUV resists was presented by Greg Denbeaux of University of Albany. EUV resist exposures are fundamentally secondary electron chemistry and not photon chemistry. He measured PAG decomposition reactions per incident electron. His preliminary calibration of 2.3 PAG reactions per incident 80 eV electron is in reasonable agreement with previous measurements for this material.
  • Charlie Tarrio of the National Institute of Standards and Technology (NIST) described round robin tests organized to ensure that all worldwide sites testing for resist outgassing provide consistent results. Initially there were four orders of magnitude difference in measurements at four sites for four resists. Potential reasons were chamber geometry, ambiguity in interpreting thickness profile and dose to clear measurements, and the temperature variation in labs. However, when fully analyzed, the data from round robin agrees well.

Panel Discussion and Workshop Survey

At the end of the workshop, we conducted a survey to find what participants had learned, and gathered their opinions about the latest status and challenges.

In response to “When do you expect to see the insertion of EUVL in HVM?” most people listed 2017 as the likely insertion date.

Most people believed Source to be the #1 issue (~60%) followed by Mask Defectivity (25%) and Resists (15%).

In response to the question, “What projects can be conducted at universities, national labs and at consortia level in the pre-competitive arena to help improve readiness of EUVL?” most believed mask related projects are the most feasible, followed by source, resist, modeling, lasers and optics. The irony is that there are hardly any source related projects in progress in these places, despite it being the greatest challenge.

Participants found that the #1 benefit from the workshop was that they were able to find out the latest status of EUVL technologies because the key players in the EUVL field were on the agenda. Participants were happy with the topics covered in the workshop and listed FEL and etched mask for high NA as topics they found new and interesting.

In the panel discussion, a couple of interesting points emerged. The first was that at 7 and 5 nm nodes, EUVL single exposure option is expected to run out of steam and at that point high the NA option is still drawing considerable interest in addition to double patterning.  Toshiba’s high NA mask etch proposal looks interesting, as it will allow us to potentially bypass difficult decisions about mask size and throughput. I had a discussion with Prof. Oh of Hanyang University during the poster session; he said his simulations show that one can even stand to gain few percentages of mask reflectivity. The second point was that with high NA option will require more power, and it is wise to consider options other than current LPP sources. Toshiba proposed consideration of FEL as an alternate technology for >250 W EUV sources.

Summary

In the workshop, we saw results on the continued progress of Gigaphoton’s and Cymer’s sources in labs. Cymer’s 40 W sources are now deployed in field. Gigaphoton is expecting to deliver their sources in 2015. I believe that this work is continuing to increase the source power available to EUVL scanners in field to the specified levels. ASML’ s press release last week on Q2 2014  performance results reiterated their goal of 500 wafers per day productivity by the end of this year, which corresponds to ~ 20 wafers per hour or ~ 20 W of source power. This is a fairly modest goal in my opinion, and based on source performance data from their labs that I have seen, I expect it to be achieved.

FEL is proposed as the new technology for sources going beyond 250 W, and it is time to start a good discussion on various design options and cost of ownership for this technology.  I hope to achieve this objective in the upcoming 2014 Source Workshop in Dublin (November 3-6, 2014). (www.euvlitho.com)

The lack of standalone commercial actinic inspection tools for patterned mask (mostly due to the lack of commercial metrology sources) is encouraging researchers to develop alternate methods and tools that can provide interim solutions for defect inspection, as we saw from Hyogo University and National Taiwan University. Actinic inspection will be needed and we need to see efforts to support development of metrology sources for actinic inspection, in order to enable tools for HVM.

Toshiba had some new solutions in their keynote presentation. The solution of etched high NA mask caught my attention – maybe this will allow us to keep 6” masks without sacrificing the throughput. FEL for the first time was mentioned as an option for HVM by a chip maker and now details of various designs need to be discussed so that cost of ownership can be assessed.

Overall, it was a good workshop with good discussions that provided a positive outlook on continued development efforts to get the tools ready for HVM.