EUVL Focus

2018 SPIE Advanced Lithography – EUVL Conference Update

By Vivek Bakshi, EUV Litho, Inc.

The 2018 SPIE Advanced Lithography meeting was held from February 25 to March 1, 2018 in San Jose, CA. As in the previous year, I will first give a high level update and then a summary of the status of EUVL, pointing out notable updates, list most interesting papers from this year and new additions to the current list of EUVL challenges.

An additional commentary on SPIE AL meeting will follow next week, giving my opinion on a couple of topics. In a separate blog, I will publish an updated list of technical challenges at all nodes, as this blog already is getting a bit too long.

  1. High Level Updates


  • Source power is at 250 W, with industrial version of source at a new record of 140 WPH (without pellicle). Scanner availability is still at 65%, with plans to ramp that up to 75% this year and 90% in 2018-19-time frame. 245 W pellicles are confirmed, so pellicle is no longer a red-flag item.
  • The APMI tool is still missing and is very much needed by 5 nm node. I heard several rumors of suppliers working on this tool now.
  • An AIMS tool from Zeiss is now operational in field. Two additional AIMS tools will be shipped this year, and now there is talk about high NA AIMS tool development.
  • High NA scanner development is coming along fine, and a high NA scanner is expected to be ready after 2024.
  • 55 MET is up and had its first light last week at CXRO, so development work on 0.55 NA EUVL can now begin!
  • There was no significant update on source or optics this year. Going by the track record, I expect Zeiss to have the high NA optics ready on time or maybe even sooner. Sources eventually will get to 500 W, but work remains to increase its uptime as that is main reason for scanner downtime. Like before, this is internal engineering which will be done with time, and I expect uptime to increase slowly to deliver 90% uptime for scanner.
  • Work has begun on identifying sources of contributions to stochastics (random noise) that come from not only photon shot noise but also from mask, resist and optics. Each one is being independently addressed and there were at least dozen papers on this topic. Several papers showing progress on post-processing techniques to reduce LER were noted.
  • Lots of work is taking place on new resist chemistries, and there were more Conference papers on resist than on any other topic. Inpria has the best non-CAR resist. Work is taking on several fronts to get resist ready for 5 nm nodes. In terms of new chemistries, we noted multi-trigger resist from Irresistible Materials, a startup from UK. One way to improve resist is via sensitizers without increasing the dose. The leader in this approach is PSCAR, and now TEL and IMEC have joined the development. This gives me more confidence that this technique may get commercialized sooner than later. There were lots of papers on fundamentals to figure out how best to deal with resist stochastics, but I do not quite see a clear strategy yet. Resist will remain a hot topic in coming years.
  • There were no updates from Intel, TSMC or Samsung – which I take to mean that they are getting into the “blackout” period for competitive reasons. Most papers were from IMEC, Global Foundries and IBM. IMEC and their collaborators are now leading development efforts to get EUVL ready.
  • There was book signing during 2018 SPIE Advanced Lithography for the brand-new text from SPIE Press on EUV Lithography! I have edited this new text with contributions from technology leaders in the industry. You can get a copy from the SPIE press:

Congratulations to all contributors!

  1. Current EUVL Status

Source: 245 W has been integrated in the scanner for a 140 WPH throughput. 250 W will allow 150 WPH throughput. Cymer has been able to convert a 250 W prototype source to an industrial version in a year, with three-day continuous run demonstrated. There was no separate update for Cymer’s sources this year in oral sessions.

Scanners: NXE3400 has achieved 140 WPH using 246 W source and no pellicle. Run was conducted for full field (96 fields) with 20 mJ resist. With pellicle, the same setup can produce >100 WPH. It was noted that in 2014 throughput was only 10 WPH, and now it is 140.

CDU for this test was 0.5 nm and overlay of 1.9 nm. Otherwise, CDU is 0.3 nm, 13 nm dense and 16 nm isolated lines, with < 6nm focus stability. Machine to machine overlay (MMO) is 1.5 nm. This can satisfy requirements for the 5 nm node.

Current uptime is 65%, with planned upgrades to increase it to 75% in 2018 (Uptime data was shown in an uncalibrated Y-axis plot, so this is my best guess). Plan is to have 90% uptime required for HVM in the 2018-19-time frame. So, it seems like this area still needs attention to get EUVL ready for HVM.

Ten scanners were shipped in 2017, and 20 are planned for 2018. Model NXE3400C planned by 2020 with 155 WPH throughput.

High NA scanner: High NA switch to 0.55 from 0.33 will enable two nodes’ worth of shrink in features. High NA offers improvement in CDU, higher effective throughput (up to 185 WPH), 40% smaller features with the same exposure latitude, but with much smaller depth of focus. Increase in throughput is obtained via an increase in mask and wafer stages. Although the high NA tool will deliver 2x to 3x power, the power density at the pellicle will remain the same, due to an increase in slit size. The tool also will have wafer cooling. Higher NA tool also has a smaller mask 3-D effect due to a smaller angle of incidence. 3D effects in tool will be addressed via sub-resolution assist features (SRAF), source mask optimization (SMO) and high-k absorber. As high NA will require stitching of two patterns, something of concern to some, it was demonstrated successfully for 24 nm dense contact holes on NXE:3300. The area stitched was black border.

The high NA tool will need 2x improvement in wave front measurement accuracy, and 2x larger mirrors. The size of high NA optics and associated metrology has resulted in a need to build new fabrication facilities at Zeiss with much higher ceilings. High NA fabs also will need higher ceilings. In summary, the feasibility phase is over for high NA EUVL scanners, and the construction phase has begun.

Insertion in HVM: Noted by several speakers and reported in press over last several months- TSMC will have node N7+ in 2019 and N5 in 2020. Samsung will have EUV in HVM first (late 2018 or early 2019 according to press reports). GlobalFoundries and Intel are expected to have ~2019 start.

Masks: Mask defectivity is currently acceptable for 7 nm node insertion. No update was provided on mask blank defectivity, as the focus has moved to defect avoidance and repair.

Mask Pellicles and Scanner Cleanliness: Mask pellicles are needed due to particles falling on mask during manufacturing, but cleanliness has improved (Initial insertion for foundry logic will use EUVL for via and contacts only, and they can use it without pellicles due to small pattern density).

Scanner cleanliness has improved to 6 particles per 10 K wafer swaps from 50 particles per 10 K wafer last year. This was achieved via hydrogen curtain, flushing, and POD parts cleanliness. The goal of one particle per 10K wafers is possible in the near future. It will be nice not to have to use pellicles.

Pellicles can now take 245 W sources. Offline tests for 300 W for >10 K wafers have been confirmed and tests for >400 W sources are planned. Current transmission of pellicle is 83% with a target of 90%. Number of defects on pellicles is zero for particles > 10 microns (good to note that it was 400 in 2017 – so great progress).

Actinic Mask Defect Inspection: AIMS tool has been delivered and this year it is working in field just fine. Two new AIMS will be delivered in 2018. New results were revealed from Lasertech on their blank inspection tool. No news on APMI tools yet, except rumors on some new tools coming soon.

Optics: Optics for 0.33 NA has been ready for many years and construction is in progress for chambers for high NA tools at Zeiss. Metrology tools for high NA are being assembled. There has been clear progress since 2017.

Resist: Latest performance results at PSI show 12 nm resolution (half pitch) at 55 mJ doe using Inpria resist and CAR with 3.4 nm and 5.7 nm respective LWR. Inpria resist can resolve up to 10 nm HP at 70 mJ dose with high LER. See Notable Updates below for additional comments on this topic. 

  1. Notable Updates
  • Jan van Schoot and E.S. Rodenik of ASML gave an extensive update on high NA tool development and NXE 3400, respectively. A summary of results is captured above in Current Status of EUVL.
  • Yan Borodovsky (ex-Intel) in his plenary talk pointed out that edge placement error (EPE) correction tapeout tooling needs to be included in tracking EUV infrastructure readiness. He discussed the presence of stochastics, which he thinks may be not be addressed at 5 nm. He thinks that industry will go to 1 D for EUV for k1 value of <0.4. (Additional comments on this will appear in my next blog.)
  • Dan Hutchinson (VLSI Research) in his plenary talk portrayed a more pragmatic view of manufacturing. More on this later.
  • Stephen Hsu (ASML) in his plenary talk pointed out the need for RET for EPE control in EUV, and recommended machine learning for RET. He believes that High NA and RET will enable sub- 5 nm nodes.
  • George Gomba (GlobalFoundries) provided a comprehensive status of EUVL readiness. I liked the updated cost of ownership and cycle time benefit for EUV vs. 193iDP. He reminded us that OPC is also required for EUV, but much less than 193i. Additional new points were loss of contrast at high NA from polarization effects. Resist and through pellicle actinic patterned mask inspection are the main challenges for 5 nm and beyond.
  • We noted a paper by Hidetami Yaegashi of TEL on post processing that resulted in “CD healing,” 30% reduction in dose and 58% reduction in CDU. He claimed to have “successfully divorced” pitch narrowing “kissing defects.”
  • Yannick Vesters of IMEC investigated adding of sanitizers – two types of metal salts, which results in reduction of dose and LWR. He noted surprising results in absorption due to addition of sensitizer. He believes that sensitizers are working via an increase in secondary electron generation and acid yield, and not via increased photon absorption. He also pointed out the need for tabulated cross-sections at 13.5 nm.
  • Vesters also showed patterning results from new multi-trigger resist from Irresistible Material, a new startup from UK. Performance with 38.5 mJ resist for 16 nm HP had 3.7 nm LER. This resist has higher etch resistance than CAR, which may allow one to use thinner resists. Work is in progress to further improve this resist.
  • Seiji Nagahara of TEL showed continued development results on PASCAR, joint work with IMEC and JSR. For the process, contrast is now more than doubled and required dose is down from 50.5 mJ to 37.5, although EL and LWR remain the same.
  • Eric Mattson of UT Dallas revealed that EUV resists show negligible thermal reactivity compared to e-beam resists.
  • Michael Murphy of SUNY Polytechnic studied the decomposition of metal containing EUV photoresists, and noted via isotope labeling that radicals leave the films, but not ions.
  • Sonia Ortega of ARCNL studied how structure affects sensitivity. Work is in progress.
  • Eishi Shiobara of EIDEC studies outgassing of EUV resists – especially how hydrogen reacts with them. He noted that hydrogen forms metal hydrides in an H2 environment, which outgas and can end up on mirrors, although a very high dose of 300 mJ was needed to be able to observe any contamination.
  • Allen Gabor of Global Foundries reviewed why four sigma rules worked before (small across chip variation) and pointed out the need for ground rules based on seven sigma for EUV.
  • Yulu Chen of GlobalFoundries demonstrated aberration induced overlay errors. If aberration is different from tool to tool, then corrections may be tool specific and the same wafer may need to stay with the same scanner.
  • Luciana Meli of IBM has an interesting set of tricks to identify and reduce stochastics defects. Coating the resist with conformal inorganic film improves 30x detection of micro-bridge defects. She noted that LWR is not a good predicter of microbridges. Current on-line metrology does not catch yield lowering defects. She proposed CD control via optimized develop process. A wafer-based dose sensor was proposed, as contamination of EUV sensors can cause process unstability. This was an interesting idea. This is a pre-exposure test that can be used to identify end of lifetime for collector and > 1% dose deficit can be detected. This technique is not focus sensitive.
  • Danilo Simone of IMEC noted that lower sensitivity corresponds to lower nano failures and said we need new metrics for resist characterization to address stochastics, e.g., image analysis and power spectrum density analysis of resist roughness. Exposure latitude can be another knob to reduce failures.
  • Joost Bekaert of IMEC put vote taking lithography to practice (application for EUV was first proposed by GlobalFoundries last year). This can work as mask related defects are uncorrelated. He had multiple identical chips on the same mask, such that each chip saw an image from four quadrants of the same mask. This technique eliminated natural mask blank related defects, smaller defects but not the large killer defects. Contrary to what one may expect, overlay was improved and a 40% reduction in nano- bridges was observed. So this is definitely a new tool in the toolbox to address random defects via averaging, but of course comes with challenges for implementation.
  • Xuemei Chen of GLOBALFOUNDRIES noted that ML surface roughness of 50 pm is not a significant contributor to LWR, but mask absorber roughness is a major contributor to aerial LWR. This was a good point to note.
  • Alessandro Pret of KLA-Tencor had interesting work analyzing stochastic process variation bands for various nodes. I look forward to reading it more carefully to get all the details.
  • Victor Carballo of IMEC looked at single exposure (SE) of EUV for 32 nm node and noted that only via retargeting was there was a process window for the entire chip. SRAF increased DOF to 30 nm.
  • Weimin Gao of Synopsys touched on the important topic of 0.55 NA vs 0.33 DP for 3 nm node (metal pitch of 21 nm). He suggested 0.55 with high k absorber is the best choice for 3 nm node. This will become an important topic next year.
  • Linaghong Yin of Mentor asserted that tool specific verification may be needed due to the magnitude of EPE, but not everyone in the audience agreed.
  • Mark Kerkhof of ASML gave an overview of diffuser optics for NXE 3400. He pointed that EUVL scanners will be inserted at k1 of 0.4, and then extended to k1 0.3 before moving to double patterning or high NA.
  • Xun Xiang of GLOBALFOUNDRIES showed that pre-etch deposition can improve pattern fidelity.
  • Anuja Silva of IBM proposed Si spin-on hard mask, as lower resist thickness improves microbridges but increases line opens. She noted that higher selectivity is not always good for pattern transfer, as “good quality” films are hard to remove. So, post litho defectivity and hard mask open processes need to be co-optimized.
  • There were a couple of papers on EUV Double patterning (DP) that I need to review.
  • TNO now has a beam-line (based on Sn DPP source) that can mimic scanner conditions for optics and contamination testing.
  • Renzo Capelli of Zeiss presented results from the first AIMS tool now in field. It can be used to look at non-resist stochastics from optics, including pellicles. It allows equivalent to scanner dose emulation. He noted that transfer of mask roughness depends on imaging conditions. Two additional AIMS will ship in 2018.
  • Andreas Erdman of Fraunhofer pointed out that the best choice for reducing 3D effects in semi-dense contacts is RuTa film.
  • Lawrence Melvin of Synopsis looked at mask absorber side angle effect on patterning roughness. Angles of 95 to 100 can improve contrast, but these type of masks may not be manufacturable. These are interesting results in any case.
  • Patrick Naulleau of LBL listed several factors that affect resist stochastics (photon noise, acid generation, PAG, quencher) and explained why material effects can be larger than photon shot noise. 0.55 MET is up and had its first light.
  • Hakaru Mizoguchi of Gigaphoton Sn LPP source has 113 W at 75% duty cycle. Source now has 0.4% reflectivity loss per gigapulse, and demonstrated 43 hour operation time with 12 kW CO2 laser. His 2018 goals are 250 W, 0.2% loss per GP, >80% availability. It’s nice to see a second supplier of Sn LPP sources continue to make progress.
  • Henry Kapteyn of K M Lab’s HHG based EUV source provides 1-3 E10 photons @ 13.5nm. Sources are currently driven by 9 W lasers, which may be scaled to >28 W in the near future to give higher power. These sources provide another way to do mask inspection using CDI – an alternative to AIMS inspection.
  • Emily Gallagher of IMEC presented data on carbon nanotube-based pellicles. These pellicles can stop most 30 nm particles, have transmission of >90%, uniformity of 0.4% and EUV reflectivity of 0.04%.
  • Iacopo Mochi of PSI showed results of actinic mask inspection using CDI at high NA, which can now do inspection up to 35 nm HP features on masks. Improvement in detectors will allow us to reach 20 nm HP resolution.
  • Peter Schepper of Inpria described distribution of resist CDU at 5 sigma and found it to be Gaussian.
  • Peter Bisschop of IMEC pointed out that controlling stochastics is key to extending EUV. Photon, resists, mask and image quality effects CD quality. I need to review the paper for details.
  • Multi-trigger resist from Irresistable Material is similar to CAR, but is not a CAR. It can allow 14 nm HP resolution without quencher.
  1. New terms heard at SPIE AL
  • Kissing defects (nano-bridging of corners),
  • Line wiggle (something also previously proposed as a measure of combining LER and LWR to predict line-breaks).
  1. Most Interesting Papers 

A couple of papers looking deeper into understanding stochastics were notable in my opinion.

  • Allen Gabor of GLOBALFOUNDRIED, “EPE Fundamentals and impact of EUV: Will traditional ground-rule calculations work in the era of EUV?” (10583-5)
  • Joost Bekaert of IMEC, “EUV Vote-taking Lithography” (10583-14)
  • Renzo Capelli of Zeiss, “Evaluation of EUV Mask impact on LER” (10583-15)
  • Patrick Naulleau of LBL, “Impact of Shot Noise on EUV Patterning” (10583-39)

And for all those who care, the best reception that I attended was at Inpria. There was a full bar and my colleagues attested to the good quality of the beverages, while I enjoyed a couple of very nice “mocktails.”

  1. Additions to existing list of challenges for EUVL: Nothing new. Focus has been taken away from pellicles and sources for now, and the main challenge for 7 nm insertion is scanner uptime (same as before).

Latest on EUV Source Technology – Highlights from 2017 Source Workshop

By Vivek Bakshi, EUV Litho, Inc.

As we look forward to 2018 SPIE Advanced Lithography conference, it is good to review the current status and recent development for EUV source technology. In this blog, I present the latest status on EUV source technology from the 2017 Source Workshop, held last November at UCD in Dublin. Highlights, notable papers, list of open questions and summary of status are presented. There are lots of details that people in the source business will find valuable. I will share in my next blog the status and challenges of the entire EUVL technology.


  • I thought that biggest lesson I learned was that resist sensitivity requirements continue to be a major driver of EUV source power requirements for scanners. Initially requirements were set at 5 mJ but today acceptable resists are at 30 mJ or more. 5 mJ to 30 mJ means 6x additional power, and no other factor can drive power requirements so drastically. Thus resist alone can be a leading factor in making a difference in whether the technology is for HVM level throughput. I believe that development of EUV resists that allow error-free printing with the least amount of EUV photons is now the leading challenge for EUVL. Unless we make good progress on this front, we will continue to depend mostly on EUV sources to address the throughput requirements.
  • Source power is now at 205 W for HVM level EUVL scanners. 250 W has been demonstrated with conversion efficiency (CE) of 6% using CO2 drive lasers at 21.5 kW (capable of 40 kW) at 50 kHz, with average 41% collector reflectivity. Enhanced isolation technology, advanced target formation technology and dose control enabled this power and collector lifetime. Droplet generator lifetime is now at 4 months. In-situ cleaning with hydrogen is proving successful in removing tin with almost no microparticles for 99.6% of targets. We are seeing <0.4% loss of reflectivity over giga pulses. We can thank 8 years of engineering and lots of hard work for this progress, as pointed out by Igor Fomenkov of Cymer in his keynote speech. Today we have 375 W in burst at 50 kHZ and 400 W has been demonstrated on research platforms. I should also point out that the current 125 wafers per hour (WPH) throughput includes a gain of 8 WPH via faster wafer swap.
  • There is interest in a new type of EUV source (broadband with wavelength less than 170 nm) that I believe will be the enabler of next-generation wafer inspection. Wafer inspection is currently being used for mask defect inspection, due to the lack of commercial patterned mask inspection. We need to extend the capabilities of wafer inspection technology by reducing the wavelength of its light sources, which will bring it into VUV/EUV region. In the workshop, I presented a draft version of requirements for such sources, based on feedback from end users and integrators. Energetiq presented their source development work in 20-50 nm and KT presented their current broadband plasma sources which are currently being used for wafer inspection.
  • The contribution of National Labs to source development was evident with various references to databases from NIST, CXRO, LLNL and LANL, as well as modeling support from these institutions. ARCNL, supported by private – public funding, is now the new and leading source of research to support EUV source development. However, the most papers from a single institution were from UCD, which had the home team advantage, and ARCNL and its collaborators were next in number of papers presented in the workshop.
  • ARCL has a new and improved identification for Sn ion emission in 7-12 nm, since what was done last by Gerry O’Sullivan of UCD almost 25 years ago. Current level assignment can lead to up to 5 nm uncertainty in spectral identification. For Sn IV, new ionization potential (IP) was presented and 12 new terms for added for this ionization. Forty-seven new lines from Sn IV were identified.
  • Carolyn Larabell of LBL in her keynote speech noted progress in the development of water window XUV sources. Previously it took six hours at diamond for a single water-window exposure, and now it takes only 10 minutes with a new setup from Hans Hertz. This is a real progress from the Source community!


  • James Colgan of LANL explained the lack of complete opacity tables for modeling of tin plasma. He presented a method for speeding up calculations for opacity for practical applications. Configuration interaction (CI) gives more accurate results than intermediate coupling (IC) for Sn LPP. Also, for the calculations of opacity of Sn, both accuracy and completeness appear crucial in obtaining converged results at moderate densities.
  • In terms of new technology, I noted Yb: YAG lasers (1030 nm) for ps pre-pulse drivers for Sn LPP. Trumpf presented results on their development work for 600 W, 80 mJ, with M2 1.12 to 1.4, pulse length of 0.7 to 1.5 ps. Max-Planck Institute presented results of their Yb: YAG lasers, which are at 400 W, M2<1.20 with 0.85 ps pulses.
  • HiLASE presented their Nd: YAG lasers development for pre-pulse lasers results for their 10 mJ, 1-2 ps, 100 K Hz, 450 W systems.
  • Gigaphoton’s Sn LPP sources for HVM continue to make steady and solid progress, as presented by Hakaru Mizoguchi. Pilot 1 system is at 113 W 5% CE, 89% availability. The present system has potential for 320 W and is capable of 500 W (via 40 kW lasers).
  • Kentaro Tomita of Kyushu University, Japan noted that top-hat laser profile may help with CE. Pulse shaping is going to be an enabler of increasing CE.
  • ARCNL showed that their LPP plasma modeling calculations can be used to identify the charge state balance observed in the spectrum.
  • W. Morgan of DIFFER proposed use of liquid metal ( liquid tin) for shielding surfaces from damage in a plasma environment, as currently being explored for fusion applications.
  • Oscar Versolato of ARNL showed a difference in physics between ns and ps interaction of droplets with lasers. Pulses of ps time scale result in spherical deformation at low energies and fragmentation at higher energies. Cavitation and spallation of droplets via shock waves was demonstrated in experimental results for ps pulses. He also presented experimental data showing an increase in ion energy when pulse length is increased from 6 ns to 4.5 ps.
  • Howard Scott of LLNL pointed out that predicting trends in LPP modeling does not depend as much on details but on correct assumptions. For accurate modeling, data must cover all charge states up to 28+ of tin ions. Controlled approximations that can allow high-fidelity simulations are available. He showed how 147K levels can be reduced to 1K for faster calculations, without significant loss of accuracy.
  • Akira Sasaki of NIQRST pointed out that CO2 laser is absorbed by target particles generated during pre-pulse. Bubbles then appear inside the liquid targets and grow to break up the droplet. However, below critical temperature, particles do not form – which may be a key to reducing debris and increasing CE.
  • Klaus Bergmann of Fraunhofer had a proposal for new source material for 6. 7 nm BEUV sources. CuMgGd alloy with melting point <500 C – gives strong Mg line at 6.7 nm. He also had a proposal for further optimization of CE for DPP sources, based on more efficient use of discharge current.
  • Yusuke Teramoto, BLV Licht- und Vakuumtechnik GmbH presented an update on compact EUV source for metrology. It now operates at 15 kHz, 76 W/mm2/sr brightness, CE<1% and 3-5% pulse to pulse stability. The position stability, important for metrology sources, is now 2-5micron pulse to pulse. He may apply the same debris mitigation technique as was used for DP for these versions of his technology targeting metrology applications.
  • A new candidate for metrology source is an Li LPP source from ISTEQ. Samir Ellwi presented that source, which operates with a 1kW drive laser to give brightness of 1000+, at 2 KHZ and CE 1.2%. Shorter pulses from his source reduce the debris.
  • Duane Hudgins, ETHZ, Switzerland presented the simulation of breakup dynamics of tin droplets in LPP using fluid models. He noted that fragments spatial distribution depends on laser spot size.
  • Yasin Ekinci of PSI presented a high-brightness accelerator-based EUV Source for EUV actinic mask inspection. A source called COSAMI is designed for 100 mW, 10E9 W/, 50 ps every 2 ns.
  • In addition to EUV and soft X-ray sources, X- ray sources are gaining attention as to their potential applications in leading edge semiconductor manufacturing. Joe Kline of NIST presented an overview of requirements for compact X-ray sources.
  • Larissa Jushkin of RWTH Aachen presented results on the application of EUV metrology tools to support advanced manufacturing beyond EUVL in a paper titled “Spectroscopic EUV Reflectometry for Characterization of Thin-films Systems and Determination of Optical Constants.”
  • Eric Louis of the University of Twente reported on ML optics development to support potential insertion of FEL based sources as high power EUV sources. He proposed a shift to 12.6 nm, from 13.5 nm, for sources for FEL, as this shift may result in a 20-25% higher transmission in a scanner. However, due to associated narrow bandwidth, central wavelength will need to be kept under very tight control.
  • There were two new spectrometers presented for EUVL spectroscopy. V. Medvedev of ISAN has developed a compact grazing-incidence spectrometer for broadband SXR-VUV spectral measurements. Also, Muharrem Bayraktar of the University of Twente presented his new transmission grating spectrometer.

Open Questions

A couple of open questions were noted in the workshop. First was how non-uniform degradation of collectors will affect the imaging, and how we address this via collector design. To focus efforts on sources for wafer inspection, we need to know the wavelength requirements for such sources. How to scale the power of EUV sources beyond 500 W is also an open issue. Will alternative technologies for high power EUV sources be able to address the many requirements for lithography sources for HVM? We need to pay close attention to see what limits may appear for Sn LPP technology.


EUV source technology is now ready at 200-250 W to enable insertion of EUVL into HVM. It still has some cost of ownership issues to address, but it is very much expected for a new advanced technology. There is slow but persistent work occurring to understand plasma dynamics via modeling and experimental work. This will allow us to increase CE, allow power scaling to reduce debris and increase component lifetime. This work must continue, and I sincerely hope that stakeholders will find a way to keep national labs involved in modeling efforts, as they have the knowledge and capability to do this. I am not sure how we will extend the current Sn LPP technology in its current form beyond 500 W. We need to continue to pay attention to FEL/accelerator-based sources and work in parallel on ML optics that will be needed for these sources. I will report back on the latest on source technology after SPIE AL.

New Frontiers for EUVL – Sources and Metrology: Topics for 2017 Source Workshop (November 6-8, 2017, Dublin, Ireland)

By Vivek Bakshi, EUV Litho, Inc.

As the focus of industry and press turns to insertion dates for EUVL in fabs, I am putting my thoughts on future nodes of EUVL for several reasons. First, I see EUVL in high volume manufacturing (HVM) fabs as a done deal, with insertion starting in HVM next year. The insertion dates by leading chip makers will be somewhat staggered because of their existing plans and products, specific insertion criterion, and so on. So there is not too much news in whoever announces using EUVL in a production line a quarter or two before the others. Second, we are approaching the phase of Moore’s Law where we face some difficult challenges in extending roadmaps to 3 nm and beyond. EUVL is in the forefront, but challenges are all around. For EUVL to succeed at these nodes, we need to focus on several technical areas. These areas are ripe for R&D, and successful solutions will lead to new and improved products for those who pay attention and invest. In this blog, I will focus on EUV Sources that will enable not only EUVL scanners but also leading-edge metrology needed for EUVL at 7 nm nodes and beyond. I will highlight how several papers in the upcoming EUV Source Workshop in Dublin (November 6-8, 2017) will address these topics.

High Power HVM Sources             

Industry has decided on Sn laser produced plasma (LPP) as the technology of choice, which uses tin droplets as an energy convertor for CO2 lasers. 250 W is already here, with development in progress for 500 W sources. As we look forward to higher powers of 500 W and beyond, there are a good many challenges than require serious R&D efforts. Current conversion efficiency (CE) is 5%, with 8-9% possible. It is not so easy to get that extra increase in CE, but the benefit is enormous in terms of the need for lower CO2 power (higher scaling), more stable sources (less overhead) and less debris (longer collector and component lifetime). Each of these items is critical, and to work on them we must look closely at fundamental data for Sn, and learn more via modeling and experiments how tin converts from liquid to plasma that generates EUV, while generating debris in the process. How far we can scale plasma sources beyond 500 W is still not known. If we need 1000 W, do we do this with plasma sources or free electron laser (FEL)? We may need to move beyond droplet generated sources for Sn LPP for higher powers, and FEL proposals need further evaluations.

In the source workshop this year, we will have sessions on fundamental data, modeling and high-power sources, which provide insight on these topics. There will be papers from ARCNL, DIFFER, LANL, LLNL, Max Plank Institute, University of Tokyo and many others. We also will have updates on high power source performance from ASML and Gigaphoton.

Broad-band EUV Sources for Wafer Inspection

This is a new topic that has seen much interest recently. As actinic patterned mask inspection tools are not ready, chip makers must rely on wafer inspection to identify mask defects. Current 193 nm based technologies have their limitations in terms of extending to 7 nm and beyond, and we need to reduce the wavelength of inspection tools. A study by NIST has showed that 47 nm (and not 13 nm) is the wavelength of choice for wafer inspection at future nodes. There are several candidates for such sources, and current learnings from EUV plasma source development and its integration can be applied to these broadband sources. I was asked by the source workshop’s committee last year to come up with draft requirements for such sources so that source suppliers have more guidance. So we plan to present a draft proposal for requirements for such sources. KLA-Tencor, Energetiq and ISTEQ plan to present the status of their plasma based broadband EUV sources, which can be applied for wafer inspection. I see another version of EUV sources emerging to help extend the Moore’s Law, by supporting advanced metrology.

Lasers for EUV Source and Metrology

Last week, one of my colleagues alerted me to recent development of 46.9 nm lasers which may be applied for wafer inspection. These lasers have only a fraction of mW of power, but after seeing how well 13.5 nm high harmonic generation (HHG) based inspection prototype tools have done, I believe one ought to review these lasers in the context of wafer inspection. The source workshop also will be covering the latest on HHG lasers and their applications, which continue to be explored as an alternative to actinic aerial image metrology systems (AIMS) and potentially for other mask defect applications. In a 2017 EUVL workshop paper, Prof. Murnane showed how HHG based actinic inspection can do a good job of defect review, and we already know that Samsung is using this technology for their EUVL development. I believe that this technology can be scaled to cover patterned mask defect inspection (PMI) as well, at least for a stopgap basis, while industry works on PMI tools.

One of the other ways lasers help Sn LPP EUV sources are in terms of pre-pulse. Pre-pulse shapes the tin droplet to a larger size, which increases coupling with the CO2 laser and increases source CE. Gigaphoton uses neodymium doped yttrium aluminum garnet (Nd:YAG) lasers with picosecond pulses, while Cymer uses a wavelength from the CO2 laser itself. YAG lasers have their own advantage and it is no small task to develop 500 W ps YAG lasers for per-pulsing. We will have updates from Trumpf and HiLase on their programs to develop these ps pre-pulse lasers, which also may play a role in FEL based EUV sources.

Metrology Sources- Plasma based and beyond

Metrology sources at 13.5 nm will enable actinic patterned mask inspection. The current workhorse for industry is the source from Energetiq, and they need higher brightness for meeting HVM requirements. Many are working hard to meet the HVM metrology source requirements by plasma sources, and Ushio, ISTEQ, ETHZ and Fraunhofer will update us on the latest in their metrology sources.

What has me excited is a new concept beyond plasma. In the 2017 EUVL workshop, we heard about compact accelerator based sources that can potentially power a scanner. Now we have a proposal from PSI for a compact source for metrology that is also based on accelerator technology. I look forward to finding out more about this non-plasma based metrology source technology.

So I am looking forward to lots of exciting papers next month in the workshop that address leading edge EUVL topics, and I will report back in a future blog on what I learn at the workshop. Abstracts for these papers and the agenda for the workshop are available at

EUVL Technology Status Update

By Vivek Bakshi, EUV Litho, Inc.

This blog gives the latest update on the status of EUVL, based on data released this summer from the 2017 EUVL Workshop, 2017 Semicon West and recent announcements. This update is in the format that I previously introduced to simplify the vast amount of information from the 2017 SPIE AL EUVL Conference. It includes a short summary of EUVL Status, a list of notable updates since the 2017 SPIE AL meeting, and additions to the current list of EUVL Challenges at various nodes (complete list previously published on this site (List of challenges at 7, 5 and 3nm nodes). Another blog, “New Frontiers for EUVL – Sources and Metrology” will be published tomorrow on this site. 

  1. Current EUVL Status


Source: 250 W standalone source power has now been demonstrated at ASML (210 W in Q1 2017). Current power of integrated sources is at 148 W, corresponding to 104 wafers per hour (WPH) scanner throughput in-house at ASML. Stable 130 W power in scanner has been noted in field. In ASML lab, EUV source power is 375 W, in burst mode at 50 kHz. 200 W of stable power may be available in field in 2017 or early 2018. Source power is now meeting requirements for the introduction of NXE3400. Current source availability is at 75%, while high volume manufacturing (HVM) requirements are >90%. Lifetime of droplet generators and collectors are improving, but need further improvement to meet HVM requirements. Collector lifetime in 2016 was 1.5x better than the previous year. Reflectivity drop for collector is now 0.4% per gigapulse. Encouraging progress by Gigaphoton, a second supplier of high power HVM EUV sources. Options for EUV Sources beyond 500 W are under study. 

Scanners: Fourteen EUVL scanners are now in field. Four scanners were shipped in 2016. Specs are 0.3 nm critical dimension uniformity (CDU) and 1.8 nm overlay. For 148 W, scanners demonstrate 104 wafers per hour (WPH) throughput, with an increase of 8 wafers WPH achieved via increase of stage speed at the same source power. NXE 3300 scanner availability at >75%. The top contributor to scanner tool downtime is the exposure source.

Higher numerical aperture (NA) EUVL scanner design is now ready, with anamorphic optics (4x/8x magnification) for EUVL extension. Higher NA scanners will have smaller depth of focus (DOF) (1/3 of 0.33 NA tools), print half field – so will require stitching. Scanners will have requirements for a larger cleanroom. For defect inspection for mask for these tools, a higher resolution for actinic inspection for defect review (AIMS), mask blank inspection (MBI) and patterned mask inspection (PMI) tools will be needed.

Masks: Mask blank defects are acceptable for now via defect avoidance and repair. Mask defects > 60 nm are zero. Total defects >23 nm spherical equivalent volume diameter (SEVD) in low single digits, with actual number depending on mask pattern density. Compensation for 3D mask effects in the near term will be done using source mask optimizing (SMO) and in the longer term by using new materials for mask stacks.

Mask Pellicles: Mask defect addition during manufacturing is still a concern for chip makers. The unpredictability of adder events drives the need for pellicles. Pellicles can now withstand 140 W of source power and plans for cooling hardware are in place for a 205 W upgrade. Pellicles need to be ready for 250 W by 2H 2017. Current single pass transmission is 85%. Current fixed pellicle design needs to evolve to provide future solutions. New carbon nanotube based pellicles have been proposed from IMEC. Intel tested pellicles for >4 K wafers at 140 W with no added defects. This is a current topic of focus for readiness for HVM. 

Mask Defect Inspection: Need for AIMS, mask blank inspection (MBI) and PMI remains. Defect review is being addressed. Samsung has made its own AIMS tool for defect review and plans to use it for HVM. Tool is using a high harmonic generation (HHG) based EUV source and a scanning zone plate. Zeiss is now shipping its first AIMS tool. Actinic patterned mask inspection (APMI) tool is still missing, while MBI tools are ready for current needs. Mask defect inspection is being done via wafer inspection for now, but at a cost and with lower yield. APMI is the only red flag item for 7 nm insertion of EUVL. We need APMI for pelliclized masks.

Resist: Adequate for 7 nm node but better local CD uniformity (LCDU) required for future nodes. To address stochastics, we need increased EUV dose and increased EUV absorption of resists. EUV resists with smaller reactive volume, more uniform distribution of components, fewer components and higher dissolution contrast are needed. Lots of talk about stochastics, but I believe it will be addressed and it is not a showstopper, although it will need a good bit of work. It is important to note that resist image is only an intermediate step, and there are still several knobs available to improve the image and performance of the final circuit – which is what matters.

Need to understand the interaction of EUV radiation with resist and design resist materials for addressing stochastics. Need to address new challenge of micro-bridging (also called nano-bridging). Its relationship to dose, type of resist and linewidth roughness (LWR) is not clear. Optical proximity correction (OPC) and Litho-etch optimization may help reduce this effect.

Continued work on chemically amplified resists (CAR), metal based inorganic resists and molecular resists to support 7 nm and beyond. Out of band (OOB) filter is now in scanner that also acts to keep out resist outgassing products.


  1. Notable Updates (Since 2017 SPIE AL Meeting)


Scanner and imaging

  • >1 M wafers exposed on NXE 33x0B in fabs.
  • Meeting 5 nm logic requirements with 0.3 nm CD uniformity (CDU) (13 nm L/S) with LWR at 3.8 nm (34 mJ) and 3.2 (58 mJ).
  • Now imaging 20 nm contact holes (CH) with CDU of 1.2 nm.
  • Demonstrating clear benefit in terms of illumination for NXE3400 over NXE3300.
  • NXT to NXT matched overlay is now 1.8 nm.
  • Throughput of 104 WPH for 148 W source for NXE:3400B (at ASML – Q1 2017)
  • Faster wafer swap, transmission improvement and source power increase will enable 125 WPH.
  • Zero adders during scanner operation, with light on, for 2400 wafer exposure demonstrated.
  • Larger NA (0.55) scanner will result in reduces dose requirements and higher effective throughput (as fewer LE steps will be required).
  • High NA will also help mitigate LCDU.
  • Infrastructure already in construction at ASML and Zeiss for high NA EUVL scanners.



  • 250 W demonstrated at ASML.
  • CE is now at 5.7% at ASML.
  • >700 hour droplet generator lifetime
  • In burst power of 375 W, in lab
  • Designs now available for 1 kW EUV source based on FEL emission in compact storage ring, and these designs need to be evaluated.
  • Discussions continue for which technology will support 1 kW EUV sources: plasma or free electron laser (FEL)/accelerator based approaches. Work is continuing in Japan on FEL based sources for EUVL.



  • Pellicle films produced without defects that print on wafers.
  • Pellicles for NXE:3400B can withstand 140 W. Y-nozzle cooling is expected to extend this to 205 W.


  • Continued work on fundamentals and evaluating performance of new resists. Metal oxide (MOx) resists provide opportunity to reduce LWR via etch and enable co-integration with newer integration schemes.



  • 100x reduction in overspray reported by Veeco, resulting in reduced mask blank defect density
  • Ion beam target overspray, target nodule formation, and particle entrainment in the ion beam, are potential ultimate limitations to particle reduction in ion beam deposition (IBD).
  • Veeco proposed Biased Target IBD and Target Confined Plasma as alternate deposition technology to IBD in long term.


  1. New Additions to existing list of challenges for EUVL (Since 2017 SPIE AL meeting, please see previous blogs (Challenges at various future nodes and Update from 2017 SPIE AL)for a complete listing) and for detailed technical information review Proceedings of 2017 EUVL Workshop or Summary of 2017 EUVL Workshop.


7 nm

Nothing new 

5 nm

Need for 350 W pellicles

3 nm

Need for 500 W pellicles

2 nm

1 kW power may be needed. How far can we stretch the LPP technology (laser power, droplet generator, contamination)? What are the challenges for FEL?

What will be the pellicle requirements?

New cap layers for Mask and optics

Understanding EUV Lithography Basics and Status – Key Concepts

By Vivek Bakshi, EUV Litho, Inc.

For a better understanding of EUVL’s status, challenges and opportunities, it is important to study its fundamental components. There are several, with the main ones being source, mask, optics, imaging and resists. They are very different from those in the current 193 nm immersion lithography, and a comprehensive overview of these components is a must. Hence, in the annual EUVL Workshop we dedicate one full day to a study of fundamentals with experts. Here I will tell you briefly about them.

EUVL is basically an optical projection lithography, but with many twists. The main reason for this is the 14x decrease of wavelength to gain on resolution, while previous reductions have been much smaller, like 1.5x. This steep decrease in wavelength requires us to work in a new region of physical properties of materials, in greater depth than we have done before.

The EUV light source is the most complex part of EUVL, and it took the most effort and time to develop. This technical feat is truly doing “rocket science” in the fab. This source was a potential showstopper at one time and now it is the key enabler for EUV for today, and for future extensions. Times have changed! For scanners, we use tin based laser produced plasma sources, but for metrology many other types of EUV sources are used and few others being considered. We will discuss technology, challenges and potential of these sources and their metrology.

Inside the EUVL scanner we use mirrors instead of the lenses used in 193 nm scanners. EUV optics, once considered impossible to manufacture, today is ahead of the curve in needed performance. But there is always more work to be done to get ready for the next nodes. EUV optics and optics chain design in an EUV scanner add unique properties to EUVL patterning. Just like optics, EUV mask is also made of multilayer mirrors with several additional levels of complexity – off-axis illumination and 3-D effects to name two. We are also learning to deal with mask defects, cleaning, defect detection and now pellicles.

Patterning with EUV involves dealing with 3-D effects, flare, new illumination and unique EUV specific optics designs. It now works like a charm, but lots of effort has gone into it to. Today, a lot more work currently is being done to extend patterning to smaller nodes with higher numerical aperture (NA) scanners. EUV resists with more energetic photons have a different chemistry and patterning performance. This is making us look beyond traditional chemically amplified (CAR) resists into new chemistries and do additional fundamental research.

Another important question for many small and large, new and established suppliers for various components for chip-making, especially who arrived late to the game, is where their products, supply chains and competencies fit in the EUVL food chain. Getting to know the fundamentals and overview of EUVL status and challenges will make the picture clearer for all. As all components interact with each other, people working in one area of EUVL with benefit immensely with an overview of other areas as well. We hope that a day of going over the EUVL basics will be very worthwhile for those who climb the hill of Berkeley this year to attend the EUVL Workshop. Additional information about this EUVL short course is available at

Progress in Short and Long Term Focus Areas for EUVL

By Vivek Bakshi, EUV Litho, Inc.

Latest news on EUVL technology status is a topic of much interest to community involved in making high‑end next generation computer chips. Next month, we will have the leading EUVL suppliers, chipmakers and researchers in Berkeley giving us the updates on short- and long-term focus areas for EUVL. I would like to summarize what I expect to be the highlights and their significance for us.

Focus on EUVL is on two fronts. First is progress in the short-term focus area that will decide how quickly, as well as how effectively (throughput and cost of ownership or COO) EUVL is being used in fabs. Topics in this category are source availability (which relates to cost of ownership), pellicles and patterning status.

We will have a manufacturing update from ASML, GlobalFoundries and Intel on these topics in their keynote and invited talks. Gigaphoton (GP), 2nd supplier of EUV sources for scanners, will talk about their new collector design with a longer lifetime (hoping for a better COO). Inpria and JSR will provide updates on the progress of EUV resists. An invited talk from IMEC will give the latest on patterning performance of EUVL from their fabs – where they are working with leading chipmakers and suppliers to prepare EUVL for manufacturing.

The second topic relates to longer term progress, as EUVL is a multi-node patterning technology expected to take us to the end of Moore’s Law. Top topics are higher NA (0.55) EUVL scanner, pathways to increase power closer to 500 W and even higher, actinic patterned mask inspection (APMI) and resist performance (stochastics, LER, micro-bridging, etc.). We will have invited talks from ASML and Zeiss on optics and design of high NA scanners. Both ASML and Gigaphoton will talk about their power scaling plans, together with several papers on EUV source fundamentals needed to ensure scaling.

I am excited about the new free-electron laser (FEL) based technology from Lyncean that they claim can provide standalone 1 kW EUV Source, based on FEL. KEK from Japan is also going to report on the progress on their FEL based EUV source technology. As APMI tools using conventional EUV sources have not been ready, the focus has moved to HHG based EUV sources for enabling mask defect inspection. These tools use alternative imaging and processing techniques, which will be described in several papers. There will be a keynote talk from Prof. Margaret Murnane, whose company has been a leading supplier of HHG sources and now plans for its increasing use in the support of lithography, including mask inspection. Veeco, maker of EUV mask blank deposition tool, used by all mask blank makers, will report on the progress of their technology to further reduce mask blank defects. There also will be several papers on resist fundamentals, which is a key knowledge enabling EUV resist readiness for future nodes.

Like previous years, we expect to hear good discussions and to generate new ideas. We plan to deliver lots of new information in just two days (over 40 papers including a poster session, which is more than many other larger conferences) in a more personal and informal setting. The workshop is from June 12-15, 2017 at CXRO in Berkeley, CA. More information is at

A final note: I believe that for better understanding of EUVL – status, challenges and opportunities – it is important to study its fundamental components. There are several components (source, mask, optics, imaging and resists) and they are different than current immersion lithography. At least a comprehensive overview of these components is a must. Hence, in the EUVL Workshop we dedicate one full day to study of fundamentals with experts. So please look for my next blog, “Understanding EUVL Basic and Status – Top Key Concepts,” at this site for further details.

Further Thoughts from the 2017 SPIE AL EUV Lithography Conference

By Vivek Bakshi, EUV Litho, Inc.

Stochastics, Lent, Reporting on Conferences, Reality of Things, and a New SEMATECH

In the previous blog, I listed technology status and would now like to discuss a couple of topics in detail. During last year’s SPIE AL conference, the message for EUVL was “Not If, but When.” This year the message was “Not If, but When and How Much Volume.” It was nice to see the technology that I bet on so long ago coming so far and doing so well.

Stochastics and LWR – Why This is not the End of EUVL and Optical Projection Lithography

The stochastics of photons and material were in the focus during the conference. One presenter even called it the cause of the “end of EUV and lithography.” Line width roughness (LWR), or the non-uniform and wiggly shapes of lines that form tiny electrical wires, affects the electrical properties of the circuits that we are working to produce in the end. Although these properties are better for circuits made with EUV compared to multiple patterning, EUV has a serious stochastics challenge as there are 14x fewer photons. I believe that that stochastics will be addressed in some ways and we must remind ourselves that our goal is not “patterns on resists,” which is an intermediate step, but to make “tiny patterns” in the material under the resist. We can beat the apparent limit of physics in how nicely we can transfer the image from mask to resist by finding solutions after the intermediate steps, as I elaborate on below.

First, LWR is not a new story. Back in the nineties, when 193 nm lithography was being developed, I was working in the ATDF fab at SEMATECH developing etch processes. I was told by many that LWR would kill 193 nm litho, as printed lines indeed looked terrible on resist, as well as when those images were transferred to the material below to form lines and contacts. I went to the library (yes, in those days you actually went to the library) trying to figure out the source of this problem, but did not get any clues. In the end by trial and error, I found that a special post-resist patterning etch, initiated before the main etch, could clean up the pattern and drastically reduce LWR. I published a paper on it and did not think much of it at that time. This post-processing of resist patterns, now combined with post-litho rinses, new underlayers, new resist chemistries, litho- dep- etch optimization, flexible pupil illuminations, and innovative mask optical proximity correction (OPC) tricks, are among several knobs available to turn down LWR. Again, remember that resist image is only an intermediate step to what we are trying to do.

At this point, we need to remind ourselves that the Rayleigh criterion of resolution limits how small we can print using a given wavelength. However, we would not be printing what we can today if we had stopped at this resolution criterion. We have been overcoming this limit via OPC and other tricks, and the factor that quantifies our capability to print smaller is called k1. A whole industry emerged around how to take k1 as low as possible. When we approached the diffraction limit of 0.25 for k1 value, it was overcome by multiple patterning and the process continued. Eventually, to continue to print smaller and smaller in the quest toward atomic-level patterning, Litho needs to work together with deposition, etch and metrology. This is already happening, as demonstrated by several papers that showed joint development with etch suppliers.

I propose that the industry develop another factor like k1 (maybe call it s1) to measure how much we can reduce the effect of stochastics, with our goal being low s1 processes.

It is worthwhile to say a few things about Moore’s Law and its projected end by many. I believe that Moore’s Law in its true spirit is not only about physical scaling of the transistors, but also about the scaling of technology to allow ever-increasing information processing. I see transistors as “units of information processing.” We will get to the limits of the current mode of scaling at atomic level patterning with circuit parameters that cannot be gainfully further improved, but that is not an end to scaling of the speed of information processing. In the end, we must switch to different technologies like quantum computing to continue the pace. However, I see no end in the next decade for the current form of scaling. Let us not forget that developing technology for scaling is not cheap, and not without lots of effort.


Ash Wednesday usually falls during the SPIE AL conference. Cathedral Basilica of St. Joseph is around the corner from the Fairmont in San Jose, where I usually stay. It has a beautiful interior and is worth a visit. I usually walk the blocks around the church until I get my required steps on Fitbit, and ponder on what I am going to give up this Lent – things that I very much enjoy and have not worked for me. This year, it surprisingly appeared to me that the trade press was also observing Lent and had given up mockery and negative coverage on EUVL, which usually starts on Sunday after Nikon’s Lithovision meeting, even before the start of the actual SPIE AL conference. It was unusually quiet this year on reporting. 

Reporting on Conference News

Toward the end of the week, there were some press reports which contained some inaccuracy. During the conference, one keynote speaker complained to me that he was incorrectly quoted by the media. Another keynote speaker was widely quoted as saying something that was not said in the presentation.

I do not blame the press fully for this, as there is an inherent difficulty in news reporting of technical conferences. Those who are familiar with scriptures know this is a challenge that humanity has faced since ancient times –reporting on complicated things from a distance. The Bhagwat Gita starts with the inquiry of the blind king Dhritrashtra, who asks an expert, Sanjay, to report on what is happening in the far away battlefield (dhramshetre kurushete… kim akurvat Sanjaya – in the battlefield at Kurushetra, dear Sanjay, tell me what happened?). It’s interesting to note that Sanjay himself was not at the battle and had to rely on other means to tell the story – such is the case for many of us who are basing their reports on what is being told by someone in the conference. I cannot blame the press too much, having myself missed on a couple of points now and then. 

Reality of things – Lessons from Zen with Relevance to our Industry

As my Zen teacher says, We like the idea of things but not the reality of things. Ordinary coping is an attempt to shape our experience to always match our idea of things. If our experience maps onto our precious idea of things, this is called ‘happiness’ or ‘satisfaction’— getting what we want. This, we are taught, is the purpose of our lives and where we will find real meaning— it is the foundation for enjoying success.” In Zen training we practice turning toward and engaging with the bare reality of things. He further adds, “We are not continually trying to shape ourselves or the world to fit our idea of things. We are meeting things just as they are and yet working with them as skillfully as we can. Zen practice encourages and supports this skillfulness.”

When the industry got to immersion lithography, the biggest challenge was how to get rid of bubbles in the water. We certainly need to do a lot more and solve problems on many technical and infrastructure fronts. EUVL indeed is complicated, as it not only involves a new type of scanner but also changing the infrastructure for mask, resist and modeling. Materials, high temperature plasmas, lasers, contamination, fabrication and metrology— you name it. Moore’s Law did not say that scaling is going to be easy or inexpensive– it just said that it will happen.

I may be the only person in the world who believes that “EUVL IS NOT LATE,” and that “WE HAVE DONE WELL” with EUV technology development. Let us not forget how much time it took us to get immersion fully working, even though we had many fewer problems. The investment now is going to pay off. Chip makers know best, and so have decided on EUVL.


One last thing. During the conference I ran into Mark Melliar-Smith, ex-CEO of SEMATECH. it was a nice surprise, as I thought he had retired some time ago. I had just finished putting up an award on my office wall that I got from him many years ago. Seeing him reminded me of good old days of the semiconductor industry, when companies got together to address infrastructure challenges and consider technical challenges where success was not guaranteed. We saved money and tackled big challenges. It had to be done then, and later on we got away from the idea. It may be time to think about a new SEMATECH regarding efforts to extend Moore’s Law. In my previous blog, I listed many things that a New SEMATECH (if we ever have it again) could do, like considering stochastics at the 5 and 7 sigma levels, new resist chemistries, and new types of sources such as those proposed by PSI. We will not get zero defect mask blanks without considering new materials, ultrafine polishing techniques and contamination control options. Chip makers (it is usually Intel which spends more than others) cannot do this alone, and suppliers cannot afford to look at these challenges on their own, either. If we want to pursue new frontiers to continue pushing Moore’s Law forward, we need a new consortium like SEMATECH. I do not mind wishing for things, as that is the first step for things to happen! I leave you with a favorite quote from the Persian poet Hafez:

“I should not make any promises right now,
But I know if you
Somewhere in this world –
Something good will happen.”
― Hafez


2017 SPIE Advanced Lithography – EUVL Conference Update

By Vivek Bakshi, EUV Litho, Inc.

To simplify the vast amount of information from the 2017 SPIE AL EUVL Conference for my blog, I have adopted a new format. It includes a short summary of EUVL Status, a list of notable updates, and additions to the current list of EUVL Challenges (previously published on this site). An additional commentary will follow this blog.

  1. Current EUVL Status 

Source: Current power of 148 W corresponding to 104 wafers per hour (WPH) scanner throughput in-house at ASML. Stable 130 W noted in field. 375 W in lab EUV sources in burst mode at 50 KHz. 200 W of stable power is possible in field in 2017. Source power now meeting requirements for introduction of NXE3400. Current source availability at 75%, needed at >90%. Droplet generators and collector lifetime improving but need further improvement.

Scanners: Fourteen EUVL scanners in field. Four shipped in 2016. 0.3 nm critical dimension uniformity (CDU) and 1.8 nm overlay. 148 W and 104 WPH with increase of 8 wafers per hour (WPH) achieved via increase of stage speed at the same source power.

Masks: Mask blank defects acceptable for now via defect avoidance and repair.

Mask Pellicles: Mask defect addition during manufacturing is still a concern for chip makers. Pellicles are at 125 W and need to be ready for 250 W by 2H 2017. 

Mask Defect Inspection: Samsung has made its own AIMS tool and plans to use it for high volume manufacturing (HVM). Tool is using HHG based EUV source and a scanning zone plate. Zeiss is now shipping its first AIMS tool. Actinic Patterned Mask Inspection (APMI) tool still missing. Mask defect inspection via wafer inspection for now, at a cost and with lower yield. APMI is only red flag item for 7 nm insertion of EUVL. 

Resist: Lots of talk about stochastics, but I believe it will be addressed and it is not a showstopper. Important to note that resist image is only an intermediate step and there are still several knobs available to improve the performance of the final circuit – which is what matters.

  1. Notable Updates 

Scanner and imaging

  • Increase of throughput by 8 WPH via greater stage speeds is first such increase, with more to come. Now expect source power of 210 W to give 125 WPH instead of 250 W (increase in throughput via stage speed improvement)
  • Extension of EUVL to low k1 may be more difficult than for 193i. Discussion of various factors and how to address them has started.
  • More enthusiasm for high NA scanner, as it can help with line width roughness (LWR) and extension to lower k1. Detailed checklist of High NA challenges from Samsung.
  • Data showing that around 5 sigma errors deviate from standard distribution. We do not understand error distribution behavior at 5 to 7 sigma (it is no longer a normal distribution). We now need to print one trillion vias in one exposure with no open! 3 sigma is no longer enough.
  • Closer cooperation among litho, etch and deposition is the way to reduce EPE and address stochastics. Work has already started.
  • Scanner to scanner variation higher for EUVL than for 193i. How to address this in optical proximity correction (OPC)? Will this lead to scanner specific EUV masks?


  • Need to better understand source power requirements for 3 nm and beyond. How much additional help we will get from scanner for increasing throughput? Is 500 W enough? Will we need additional power?
  • Power scaling to 500 W is still lots of work and not a done deal as conversion efficiency decreases at higher pulse energy (favored method for power scaling). 


  • Introduction at 7 nm planned at 20 mJ dose
  • Micro bridging (aka nano bridging) of resist is a new challenge reported by several people. Its relationship to dose, type of resist and LWR is not clear. Some said that this may become bigger than LWR issue. Papers showing OPC and Litho- etch optimization can help reduce this effect.
  • Continued work on chemically amplified resists (CAR), metal based inorganic resists and molecular resists to support 7 nm and beyond.
  • Out of Band (OOB) filter in now in scanner that also acts to keep resist outgassing products out.
  • Sigma alone may be insufficient to characterize LWR. New additional variables needed? 


  • Replacement of current mask absorbers by Ni to improve imaging. Continued review of new mask structures with improved imaging potential, but patterning challenges exist for these new stacks.
  • Need source mask optimization to address 3D mask effects.
  • High sensitivity to Pellicles defects for small pupil fills imaging
  • Need for further analysis and reduction of defects in the scanner, that end up on masks, generated during manufacturing.
  • Current fixed pellicle design needs to evolve to provide future solutions.
  • New carbon nanotube based pellicles from IMEC
  • New APMI design from PSI/ETH, supported by small synchrotron based EUV source.

New terms heard at SPIE AL

  • Etch Color, CD healing, Black Swans (at seven sigma), Vote-taking Lithography (resurrection of a 1986 idea to move away from 100% defect free mask requirements), nano bridging and micro bridging of resists, and Tone inversion.

Most Interesting Papers

  • Couple of papers on stochastics – Line edge roughness (LER) performance targets for EUVL (10143-10) by Tim Brunner of GlobalFoundries and Lithographic Stochastics – extrapolating to 7 sigma (10143-31) by Robert Bristol of Intel.
  1. Additions to existing list of challenges for EUVL

7 nm

Nothing new

5 nm

Micro bridging of resists

Error distribution at 5-7 sigma 

3 nm

Power scaling to 500 W and beyond

Micro bridging of resists

Error distribution at 5-7 sigma

Areas of Focus and List of Challenges for EUV Lithography at 7nm, 5nm and 3nm Nodes

By Vivek Bakshi, EUV Litho, Inc.

As we look forward to 2017 SPIE Advanced Lithography Conference in San Jose next week, the focus once again will be on EUV Lithography, its readiness for manufacturing and plans of chip makers for starting to use EUVL in their fabs.

Insertion is planned from 7 to 5nm nodes by chip makers in coming years. The areas of focus at 7nm are mostly related to productivity and uptime goals of sources in addition to pellicle. The 5nm insertion has few other areas come into focus where more work is needed like actinic inspection, resist readiness and mask blank defectivity – although none of them is a showstopper.

List of challenges pick up lot more at 3nm node, as we consider high NA scanner, corresponding newer design for EUV masks and need to for upto 500 W of source power. A detailed list of these challenges is worth a review and is now published at the website as topics for 2017 EUVL Workshop in June 2017. I will be updating this list after as well as sharing my opinion on the latest with EUVL in coming weeks after this year’s SPIE AL meeting.

Bringing you Holiday Cheers – Courtesy of Moore’s Law

Vivek Bakshi, EUV Litho, Inc.

Author’s preface: This article is a departure from my usual high-tech language, because I think our industry needs to do more to educate non-technical readers about how their treasured electronic devices got to be so cheap and powerful. Our success in realizing Moore’s Law has been one of the greatest achievements in modern science, and we must continue doing all we can to continue that progress. Please feel free to share this essay as a holiday gift to anyone in your life who benefits from the achievements of lithography.

For many, our Christmas holiday cheer is wrapped around getting the latest gadget that brings us more power to do things than we had the year before ‒ be it a new iPhone, iPad, laptop or some other high-tech gizmo. Added to this annual ritual, which we now intuitively expect but do not quite notice, is that we pay less or the same for these gadgets than we did in previous years – even though they may run twice as fast and store three times as many photos and videos. At the heart of this happy surge are the computer chips that grow more powerful every year without increasing their price. I would like to tell you how we in the computer chip industry do this, and what it will take to continue this trend in the coming decades.

Technology was not always like this. Growing up in the early 80s in India, where my dad worked for the telephone company, I remember that when we got a new phone it was the same rotary dial model with just a new exterior body, and maybe a new color. If today’s technology were moving at the same speed as then, we would only be getting a new cover for our iPhone or a new computer mouse for Christmas, and not more powerful gadgets.

To understand this phenomenon, we need to look at the leading-edge computer chips that are the heart of all these tools, made by leading chipmakers like Intel, Samsung and others. Inside these microchips are tiny transistors and other circuit elements that do the work. The reason these devices can deliver more power every year at lower cost is because the advancement of computer technology is guided by Moore’s Law, named after Gordon Moore, co-founder of Intel Corporation. Moore proposed this law in 1965, saying that number of transistors per square inch would double every two years or so.

We have been able to follow Moore’s Law so far by making transistors and other circuit elements smaller every year. Making computer chips takes many steps, the most critical of which are embodied in a process called Lithography, which involves printing the images of circuits. To print smaller and smaller transistors, we need to be able to resolve the printed images. British physicist Lord Rayleigh (1842-1919) pointed us to “knobs” that we can turn to resolve ever-smaller images. Prominent knobs are color of the light for printing (wavelength), design of optics (numerical aperture) and printing under something more dense, like water. We also have also learned lots of tricks (called optical proximity corrections and multiple patterning) that let us keep on printing smaller and smaller features.

The current technology of choice for advanced printing of computer chips is called 193 nm optical projection lithography, which involves a zillion optical tricks and repeats the printing process three or four times to make one image. However, 193 nm has been running out of steam for some time. This means that either we cannot make computer chips more powerful by just shrinking the size of features, or the cost of doing so will be a lot more. Neither of these are acceptable solutions, and that is where Extreme Ultraviolet Lithography (EUVL) comes into play.

EUVL promises to extend Moore’s Law by changing the color of light used for printing – from current 193 nm light from excimer lasers to 13.5 nm light from plasma sources. Alas, we cannot see either wavelength with our unaided eyes. This switch of color came with big physics challenges as EUV Light, with its photons of 14x energy, interacts with matter very differently than photons from excimer light. This change has resulted in a massive amount of work over many decades on light sources, optics and photo-sensitive chemicals for developing images. For these reasons, EUVL has taken many decades of worldwide effort and investment and is now expected to be used by leading chipmakers by 2018- 2020 time frame.

We would certainly be lost without the ever-more powerful computer chips that we are now used to having at our disposal every year. So now you know whom to thank for your new holiday gadgets, and you can rest assured that they will keep on working to ensure the benefits of Moore’s Law will continue for years to come.