Author Archives: sdavis

New Benchmark Established for EUV

I received this news from Dan Corliss of IBM today and it is reproduced below. Dan is the EUV Development Program Manager for IBM. As the previous goal for ASML scanner for 2014 was 500 wafers a day, this is definitely big news. Dan called it a “watershed moment” in his LinkedIn post. Of course, we need to see this type of performance to happen longer term like weekly basis, and it needs to be repeated by several leading edge chip makers but this is a sign of good things to come. Congratulations to Dan and his team, ASML and Cymer for significant achievement. We needed this and it looks like this EUVL is finally getting ready for production!

IBM’s NXE3300B scanner, at the EUV Center of Excellence in Albany, recently completed a “40W” EUV light source upgrade.  The upgrade resulted in better than projected performance with 44W of EUV light being measured at intermediate focus and confirmed in resist at the wafer level.  In the first 24 hours of operation after the upgrade  637 wafer exposures were completed in normal production lot mode with:

- 20 mJ dose

- 83 image fields/wafer (full wafer coverage, including partial die)

- conventional illumination

This is a watershed moment for EUV as it establishes the benchmark capability of the EUV source and scanner to support semiconductor technology node development.

EUVL pic

2014 EUVL Workshop: Highlights and Summary

By Vivek Bakshi, EUV Litho, Inc.

Keynote talks

The 2014 EUVL Workshop was held late last month amid some positive highlights and lots of R&D updates. The keynote talks this year were from Intel, Gigaphoton and Toshiba.

Intel in their keynote, paraphrasing Mark Twain and Mark Bohr, said that “rumors of scaling’s death are greatly exaggerated!” I tend to agree. In terms of choices for upcoming technology nodes, Intel is doing 14nm with 193nm lithography, and for 10nm, there is an EUV pilot line in addition to the primary approach of 193i extension. Overall, Intel will insert EUV when production tools are available and affordable, which depends mostly on EUV source readiness.

In the next keynote, Gigaphoton shared their latest results of 62 W at intermediate focus (the location where power is measured for forecasting the productivity of an EUVL scanner). This was achieved via 3.9% conversion efficiency (CE) at 50 K Hz for a low duty cycle of 5%. Mizoguchi-san from Gigaphoton expected that in coming weeks via doubling the frequency, he might be able to double the source power to >100 W. After the workshop, Gigaphoton put out a press release on July 1, reporting 92 W source power with 4.3% CE. We look forward to an increased duty cycle, an increase in operation frequency to 100 K HZ, and shipment and performance at a customer site, which they said was planned for 2015.

Toshiba’s speaker, Uchiyama-san, in his keynote talk outlined interesting solutions for the extension of EUV. A high NA option, in addition to double patterning, has been outlined by the industry to allow EUVL to continue to shrink patterning beyond 7 nm. However, the high NA scanner option has been debated without a decision due to consequences for mask size and throughput. Uchiyama-san of Toshiba pointed out an option of etched mask for high NA, which will allow the use of the current mask size and throughput, hence bypassing difficult choices. To support his proposal, he showed results for etched multi-layer masks.


Cymer in their invited talk noted that NXE3100 (previous versions of ASML EUVL scanners) sources now have >70% availability with 70G pulses average lifetime, while >100G pulses are needed for HVM. Their sources for NXE3300B are now in the field and are being integrated. These sources in lab use demonstrated ~ 40 W with 2.5 % CE, 35% dose margin and a collector lifetime for >5 G pulses.  For standalone next version of lab sources, they are now at 75 W in open loop power and 70 W in stabilized mode.

Toshiba proposed free-electron laser (FEL) as a candidate for > 250 W EUV sources. They had feedback from FEL experts that FEL sources can be made even cheaper than LPP based sources. I expect to hear more details from Toshiba and other FEL experts on their proposed designs for FEL for 13.5 nm as well as the details on the cost of ownership.

R&D Progress Notes

The Workshop, with its focus on R&D topics, had quite a few good papers with encouraging reports of progress.

  • HiLASE is developing Nd: YAG lasers for pre-pulse technology to support HVM EUV sources. One of their project goal is to have lasers with 3.3 mJ pulses operating at 150 K Hz with 500 W average power and <10 ps pulse width. After starting with their project over a year ago, they now have lasers with 0.8 mJ pulse energy,  average power of 85 W 100 K Hz, with pulse width of <2 ps.
  • Efficient CO2 lasers are important for power  scaling and Koji Yasui of Mitsubishi Electric Corporation described their transverse gas flow CO2 lasers that they are developing to support Gigaphoton’ s EUV sources. These lasers have higher amplifier gain (meaning higher power), lower gas flow speed and short length to achieve stable operation (resulting in a smaller foot print), as compared to axial flow CO2 lasers. Their lasers provide 1.6 x times more power than axial-flow CO2 for the same input of 400 kW. Currently they have an output power of 21 kW (33% duty cycle); four amplifiers driven by two-line oscillator give an output pulse of 23 ns.
  • Power scaling of HVM sources also results in more tin debris, and in-situ cleaning is one of the many methods to remove the residual tin from collector surfaces. David N. Ruzic of UIUC showed his plasma based cleaning method that results in a very small reflectivity loss (1.2%) when cap layers of collector mirrors are exposed to plasma cleaning.
  • Speakers from Korea, China, Taiwan, Europe, Japan and USA presented an overview of EUVL related regional activities in their respected regions, indicating an impressive set of investments, but also outlined lack of funding for research on EUV sources.
  • Yanqiu Li and Zhen Cao of Beijing Institute of Technology presented their design of EUV objective with a co-axial objective systems of 6 mirrors (NA 0.5), 8 mirrors (NA 0.4) and 10 mirrors (NA 0.75), and an off-axis objective system of 6 mirrors (NA 0.4). They also presented a design of an EUV scanner illuminator system with illumination uniformity better than 2.5%.
  • Hiroo Kinoshita of University of Hyogo presented data on the performance of his new reflectometer. This is the largest reflectometer in the world and can measure up to 800 mm optics.
  • Yuriy Platonov of Rigaku Innovative Technologies presented data on the performance of his In-line Gen 2 system multi-layer deposition system. The system can now make depositions of up to 750 mm optics and is capable of velocity profiling for illuminator optics. This deposition system has a high throughput to support high volume production. He also has shared performance information on his new EUVL optics refurbishment facility, which can perform etch and clean operations.
  • Actinic inspection will be needed for EUVL HVM and new techniques and instrumentation are being developed. Kuen-Yu Tsai of  National Taiwan University presented a non-imaging defect inspection method with non-imaging optics hardware. His actinic inspection method estimates the size of defect features from scattering signal.
  • Rupert Perera of EUV Tech presented data on his 4th generation Reflectometer. This new version of the tool can measure reflectivity from a 5-10 degree angle with a spot size of 1.8 mm x 1.8 mm2 and 3 sigma of 0.3 %.
  • Jung Sik Kim of Hanyang University presented his design of thin attenuated phase shift mask (PSM) that helps reduce effect of photon shot noise. The modeling suggests that proposed mask design will result in improvements in image contrast, image log slope (ILS), CD uniformity (CDU), contact edge roughness (CER) and dose to size.
  • Sushil Padiyar of Applied Materials outlined progress in EUV mask clean and etch. Using wet and dry cleaning methods, he estimated that there was only 0.018% reflectivity loss per clean and for 50 cleans, measured 0.02 nm increase in Ru surface roughness. These measurements were done for Ru Cap mask blanks. For pattered masks, there was <0.05 nm clean CD loss per cleans. For EUV patterned mask etch, his company has demonstrated <2 nm 3 sigma EUV mask etch CDU and considers their tool to be ready for EUV HVM.
  • Hiroo Kinoshita, University of Hyogo, presented the latest results from his Coherent EUV Scattering Microscope (CSM). Now phase defects of 25.5 nm width with 1.4 nm height can be detected by his tool.
  • Takahiro Kozawa of Osaka University, describing studies of Stochastic Effects in Chemically Amplified Resists, gave a summary of design of materials for 16 and 11 nm nodes. He also identified the parameters that are needed for characterization of the potential materials for EUV resists.
  • Patrick Naulleau of LBNL, in his paper on impact of EUV mask roughness on inspection, noted that the roughness has significant impact on inspection and the scatterometry measures true EUV roughness. He also believes that actinic characterization is likely required for EUVL in HVM and that the system modeling points to EUV roughness requirements close to 50 pm.
  • Yoshi Hishiro of JSR Micro described his projects for the development of novel EUV resist materials for the reduction of EUV resist defects. He pointed out that High Tg resin improves resolution and LWR, and that the profile control is important for resolution. He presented results showing that defectivity improvement is possible by controlling resist hydrophobicity.
  • The role of secondary electrons in EUV resists was presented by Greg Denbeaux of University of Albany. EUV resist exposures are fundamentally secondary electron chemistry and not photon chemistry. He measured PAG decomposition reactions per incident electron. His preliminary calibration of 2.3 PAG reactions per incident 80 eV electron is in reasonable agreement with previous measurements for this material.
  • Charlie Tarrio of the National Institute of Standards and Technology (NIST) described round robin tests organized to ensure that all worldwide sites testing for resist outgassing provide consistent results. Initially there were four orders of magnitude difference in measurements at four sites for four resists. Potential reasons were chamber geometry, ambiguity in interpreting thickness profile and dose to clear measurements, and the temperature variation in labs. However, when fully analyzed, the data from round robin agrees well.

Panel Discussion and Workshop Survey

At the end of the workshop, we conducted a survey to find what participants had learned, and gathered their opinions about the latest status and challenges.

In response to “When do you expect to see the insertion of EUVL in HVM?” most people listed 2017 as the likely insertion date.

Most people believed Source to be the #1 issue (~60%) followed by Mask Defectivity (25%) and Resists (15%).

In response to the question, “What projects can be conducted at universities, national labs and at consortia level in the pre-competitive arena to help improve readiness of EUVL?” most believed mask related projects are the most feasible, followed by source, resist, modeling, lasers and optics. The irony is that there are hardly any source related projects in progress in these places, despite it being the greatest challenge.

Participants found that the #1 benefit from the workshop was that they were able to find out the latest status of EUVL technologies because the key players in the EUVL field were on the agenda. Participants were happy with the topics covered in the workshop and listed FEL and etched mask for high NA as topics they found new and interesting.

In the panel discussion, a couple of interesting points emerged. The first was that at 7 and 5 nm nodes, EUVL single exposure option is expected to run out of steam and at that point high the NA option is still drawing considerable interest in addition to double patterning.  Toshiba’s high NA mask etch proposal looks interesting, as it will allow us to potentially bypass difficult decisions about mask size and throughput. I had a discussion with Prof. Oh of Hanyang University during the poster session; he said his simulations show that one can even stand to gain few percentages of mask reflectivity. The second point was that with high NA option will require more power, and it is wise to consider options other than current LPP sources. Toshiba proposed consideration of FEL as an alternate technology for >250 W EUV sources.


In the workshop, we saw results on the continued progress of Gigaphoton’s and Cymer’s sources in labs. Cymer’s 40 W sources are now deployed in field. Gigaphoton is expecting to deliver their sources in 2015. I believe that this work is continuing to increase the source power available to EUVL scanners in field to the specified levels. ASML’ s press release last week on Q2 2014  performance results reiterated their goal of 500 wafers per day productivity by the end of this year, which corresponds to ~ 20 wafers per hour or ~ 20 W of source power. This is a fairly modest goal in my opinion, and based on source performance data from their labs that I have seen, I expect it to be achieved.

FEL is proposed as the new technology for sources going beyond 250 W, and it is time to start a good discussion on various design options and cost of ownership for this technology.  I hope to achieve this objective in the upcoming 2014 Source Workshop in Dublin (November 3-6, 2014). (

The lack of standalone commercial actinic inspection tools for patterned mask (mostly due to the lack of commercial metrology sources) is encouraging researchers to develop alternate methods and tools that can provide interim solutions for defect inspection, as we saw from Hyogo University and National Taiwan University. Actinic inspection will be needed and we need to see efforts to support development of metrology sources for actinic inspection, in order to enable tools for HVM.

Toshiba had some new solutions in their keynote presentation. The solution of etched high NA mask caught my attention – maybe this will allow us to keep 6” masks without sacrificing the throughput. FEL for the first time was mentioned as an option for HVM by a chip maker and now details of various designs need to be discussed so that cost of ownership can be assessed.

Overall, it was a good workshop with good discussions that provided a positive outlook on continued development efforts to get the tools ready for HVM.

Insertion of EUVL into fab: Challenges for 7nm insertion

By Vivek Bakshi and Sushil Padiyar

While two chipmakers are reported to be working on inserting EUVL into fabs for manufacturing at the 10nm node, many others expect to insert EUVL into manufacturing at the 7nm node or later. It takes a large infrastructure to make EUVL a manufacturing technology. So many tool suppliers, large and small, want to know when EUVL will be inserted into fabs for production and how and how much it will be used. Their business depends on these answers and some, especially smaller suppliers, are getting cold feet as delays in EUVL readiness continue. The answers to these questions mostly depend on knowing what we can expect from sources in the short- and near term, but there are many additional questions one must ask as well.

To help us develop more clarity on EUVL readiness, we are asking panelists in the upcoming 2014 EUVL Workshop (June 23-27, 2014) to respond to the following questions on whether EUVL can deliver patterning solutions for 7nm:

  1. What is the latest status for source power available for NXE 3300B? What is your opinion on source power requirements for the 7nm and 5nm nodes?
  2. Will EUV double patterning be required at 7nm? What will be required at 5 nm? Do you expect any OPC-related issues?
  3. Mask: What will be the new material requirements and mask size requirements to accommodate higher NA patterning? Do you expect mask etch complexity with new materials? How ready are masks to support 7nm manufacturing? What is the status of mask defect inspection and repair tools?
  4. Pellicle: Is a no-pellicle approach a show-stopper for HVM insertion of EUVL? What additional restrictions do you expect on inspection due to pellicle issues?
  5. What are the different device types and lithography needed at various nodes, e.g., 3D NAND, III-V Logic, post FinFET era, etc.

Dr. Sushil Padiyar of Applied Materials (AMAT) helped me prepare these questions for the panel discussion, as he has done in previous years. I look forward to a good exchange of opinions during the panel and will report the results in this blog, in addition to summarizing the many excellent papers that I look forward to hearing. The agenda for the workshop can be downloaded at my website,

State of EUVL – Challenges of HVM Introduction

Vivek Bakshi, EUV Litho, Inc.,

Most of the papers at this year’s EUVL Conference during SPIE’s 2014 Advanced Lithography program focused on topics relating to EUVL’s entrance into high volume manufacturing (HVM). The 2014 EUVL Conference also had a record number of papers – 67 oral presentations and 66 poster sessions –   for a 13% increase over last year. Although I did not see an increase in my EUVL short course students, both of my EUV books went into their second printing this year in soft cover, as the first editions in hard covers have sold out. So overall, there was a lot of continued momentum for EUVL as it moves toward HVM introduction.

Focus on Fab Matrices

In their paper, GLOBALFOUNDRIES compared EUVL and ArF immersion scanners for 20/14 nm metal lines and found equal yields for both lithography techniques. They did note an additional issue of EUV mask backside contamination, which I believe can be addressed. For 10/7 nm metal lines, they believe they need to address issues of overlay, mask defects, integration and line width roughness (LWR) through focus, in order to bring EUVL into production.

IMEC presented a preliminary cost of ownership (COO) study that concluded that at the 7 nm node, 75 wafers per hour (WPH) throughput will be needed for EUVL to show better COO than ArF immersion (ArFi) multiple patterning (MP). This throughput corresponds to 100 W of source power at the intermediate focus.

HVM-related metrics such as yield and availability (mean time to failure [MTTF], mean time to repair [MTTR], etc.) are now the focus. It was evident from the talk by TSMC, which reported ~10 W of power instead of the expected 30 W for their planned insertion of EUVL into the 10 nm node. A laser misalignment caused a source breakdown and a two-week unexpected downtime for the tool. This did not make TSMC happy, but did cause some trade journalists not known for their support of EUVL to announce that “EUVL suffers new setback” when it clearly had not. A brand new tool’s first installation in the field can be expected to have glitches and downtime; expecting anything else is not realistic. (More comments on source are given below.) TSMC also reconfirmed their commitment to bring EUVL into HVM at the 10 nm node.

Mark Philips of Intel, in his talk, outlined the 1-D grating and cuts approach of Yan Borodovsky. EUVL is the preferred choice for cuts as EUVL offers advantages in terms of number of masks and edge placement error (EPE). Intel still plans to insert EUVL at the 7 nm node in 2017, but needs a mature COO for EUVL. It will be either mix and match with ArFi MP or EUVL alone, depending upon the cost drivers. As the mix and match approach faces the issue of overlay, he presented a detailed model, developed with Mike Hanna of ASML, that identifies the root cause of machine to machine overlay values and will help minimize it. Current machine to machine overlay (EUVL and ArFi) is 5 nm but needs to be 3.5 nm at 10 nm nodes and 3.0 nm at 7 nm node. My perception is that with the amount of effort going into it, those goals can be achieved.

Hynix, in their paper on EUVL development efforts, made a comment that self-aligned quadruple patterning (SAQP) has 5x more steps than EUVL and that many multiple patterning steps take away any benefit that one can expect from it, and hence are not beneficial.

Source Technology Status

ASML currently has three NXE 3300B, HVM level scanners being installed in the field, including one at TSMC. They reported 30 W power (down from 50 W reported in the lab last year) with 100 W planned for this year and 250 W for next year. We know that TSMC had only 10 W at the time of conference. With ASML acquiring Cymer, I expected a change in how data is presented, with more realistic roadmaps. I understand that to predict the readiness of source is very hard, as there are many new technologies that may do well in the lab with a dozen PhDs fine-tuning them, but aren’t necessarily ready for the field where they have to perform 24 x 7 while being operated by technicians. Hence, it will take time to make them work in a fab.

Let me also mention Gigaphoton (GP), the other high power source supplier. In my opinion, they are ahead in technology but behind in engineering. They have a very stable 20 micron droplet technology (less debris), prepulse with dual wavelengths (less debris and higher conversion efficiency [CE]), magnetic debris mitigation (better debris control), infrared (IR) rejection collectors (improved image quality) and axial flow CO2 laser technology from Mitsubishi (1.6x more energy efficient than transverse flow). However, they have 42 W (duty cycle ?, 200 W at source and CE of 2.4%)  and 16.9 W (duty cycle ?, 78 W at source, 3.9% CE) and expect their source to be ready in 2015.

I also seriously doubt that in situ cleaning alone can remove tin debris at 250 W and am ready to bet that it will need additional techniques such as magnetic mitigation and redesign of the tin delivery approach to meet the requirements. As GP sees 0.1 nm of tin deposited per million pulses, it is a lot of tin to remove.

My personal opinion is that if we can get 50 W with decent availability in the field this year for 3300 B, it will be a great achievement. 100 W will follow over the coming years and I cannot predict yet when 250 W sources will be ready. With the data that I currently have seen, I will stick with my predictions.

For 500- 1000 W, I think it is a good idea to look at alternate technologies such as accelerator based sources. Zeiss and Helmholtz Zentrum presented a paper on free-electron laser (FEL) based sources for 13.5 and 6.5 nm. (They first presented this idea in 2012 in my Dublin Source Workshop. I plan to have a special session on accelerator based sources again this year, as I did in the 2011 Dublin Source Workshop. ) This idea has merit and although €200 M potential price tag may have scared most people, I think the cost can be brought down. It is now time to theoretically investigate various accelerator approaches and identify difficult challenges, feasibility and roadblocks.

Out of Band (OOB) Radiation

Last year I reported on top coat approaches, which have used by chip-makers to remove OOB radiation that reaches the wafer to improve image quality. However, this comes with up to a 15% loss of photons, extra processing costs, and outgassing. An alternate idea is to incorporate OOB filtering in the collector, as presented by Eric Louis of FOM Institute DIFFER. Maybe this or something similar can be added to IR rejection that GP has built into its source collectors.

Scanner Status

ASML is putting together 11 NXE3300 B tools (with three delivered) and has started work on next generation scanners of NXE3350B. These introduce a new parameter of non-correctable error (NCE) for optics. It is 0.7nm for 3300B and will be 0.4 nm for 3350B. With their flex pupil approach, they reported 16 nm L/S data with 10% exposure latitude.


TSMC reported in their talk that particles are generated during the exposure process, fall on the mask and need to be cleaned. It is not a surprise, as EUV photons generate particles when they react with background contamination. These particles are not captured in the particle adder test that was reported by ASML.  More important than deciding who needs to be responsible for cleaning the defects (OEM or chip-maker) is to come up with a solution. We already see that pellicles offer a potential solution. ASML reported 70 nm film (60 nm pSi with caps of SiN on both sides) on a frame with 82% transmission, 106 x 139 mm2 (full size in a holder) and 1.4% average variation in intensity across the pellicle. It has been tested for 120 W of source power. There is still some possibility of generation of contamination between pellicle and mask, addition of particles during installation, lifetime and OOB reflectivity of pellicles. I expect these topics to be addressed with time.

High NA Scanners

Starting at 7 nm, a decision has to be made on going with either high NA of 0.5, or with EUV at 0.33 NA and double patterning. At < 7 nm, scanners with >0.33 NA will be needed. High NA will increase the incident angle on mask, resulting in excessive H-V bias and poor image quality. So the industry has to decide on various potential options, which include going from six to eight mirrors in scanners, mask size change from current 6 to 12 inches, and quarter- to full-field exposure options. Currently there is no common ground among OEMs, mask makers and chip-makers, but a consensus is expected to be reached by year-end, as pointed out by Patrick Kearney of SEMATECH, who presented COO for various options.

Meanwhile, Zygo has made significant progress in building high NA optics (0.5) for a micro exposure tool. Wave front error (WFE) is < 1 nm and flare is 2.5% (0.5 nm). Kevin Cummings of SEMATECH presented his plans for getting the tool ready this year for 9 nm exposure with 5 x magnification. I believe that a high NA approach will be demonstrated without issues – it just needs to be decided what other options on scanner and masks we will go with.

Toshiba called for development of 6-inch masks that can support 0.55 NA with 4x magnification and full field exposure. However, I do not know yet if we can make them to deliver acceptable imaging quality.


Mask papers mostly remain focused on addressing defectivity, with excellent contributions from SEMATECH on many fronts. Efforts in mask cleaning are making progress with reduction in damage from cleaning. What I found most interesting was the Pareto of sources of defects on substrate and masks. The planned Veeco tool upgrade will help address many of the mask blank defects. Mask defects can be either cleaned, repaired or avoided during mask patterning to provide acceptable mask yields. To avoid defects, mask patterns can be shifted or rotated during patterning. Puneet Gupta of UCLA had a third option calling for independent shifts and rotation of individual dies, which can yield 60% better yield for up to 40 printable defects (taken as 2 nm high and 50nm wide in his theoretical study). It will be a difficult solution to implement, but will it be more difficult than alternative options?

The AIMS tool from Zeiss is now taking data and can review the printability of 30-45nm defects (7-11nm at wafers) with plans to deliver the tool in 2015.  SHARP microscope is up and already supporting customers at Lawrence Berkeley National Laboratory (LBNL).

For patterned mask inspection there was no update from KLA on the actinic pattern mask inspection (PMI) tool, and in general I heard no great push for getting the actinic PMI tool ready either. On the other hand, e-beam inspection for patterned mask is making good progress, with Ebara (funded by EIDEC) reporting capability to detect 28nm defects, and 16nm detection capability coming soon. IBM reported good progress in e-beam based mask inspection and using the Hermes Vision tool, and can detect <10 nm defects on wafers.

I understand that without bright mask metrology sources, tools for actinic inspection for mask defects are not going to make progress in throughput. Although we can do the job via non-actinic inspection for now, it will be not wise to continue accepting a lack of progress on metrology sources, as these tools will be needed at 7nm and below.


Resist is finally coming to the rescue of lack of source power and will become a key enabler of EUVL. It is also clear that in addition to resolution, LER and dosage, outgassing requirements must be met by resists.

I found a good bit of progress on the topic of outgassing: a paper by TSMC on prediction of outgassing of a given CAR resist; Tarutani (Fuji file) noted that outgassing is related to deprotection mechanism; progress in identifying reasons for variability of outgassing measurements in benchmarking by NIST; and analysis of non-cleanable (by hydrogen) contamination by EIDEC. As it turns out, iodine is the biggest culprit, with sulfur a distant second, as the reason for non-cleanable contamination. U Albany showed that outgassing is directly proportional to 5 times Eo (dose to clear) and the top 20 nm of resists contribute to outgassing. IMEC showed that in outgassing studies, electron beam (EB) and EUV studies can be made to be equivalent for a given setup.

There was a great deal of progress reported on understanding and improving the chemically amplified (CAR) resists by Osaka, Intel, Dow, JSR and TOK, but I found results on non-CAR resists to be even more exciting. There was impressive work on non-CAR resists and I will discuss only those with low dosage requirements. Most are based on various metal oxides, added to increase EUV sensitivity.  Impria presented resists with HfO2 with 3-4 x sensitivity and with SnO2 5-8 x sensitivity greater than CAR. SUNY at New Paltz also showed results for resists with various metal clusters in a large study. The Cornell (Chris Ober) group presented results of 1.4 -1.6 mJ of ZrO2 with 5-7 nm LER and with HfO2 with 2.5 mJ sensitivity with 3-5 nm LER! I found this to be the highlight of the conference, although potential contamination from various metals still needs to be evaluated The Indian Institute of Technology (IIT), my alma mater from India, had a paper on non-CAR chemistry with 10 mJ resist with 1.8 nm LER.


Status of my Lotus bet with Lithoguru:  Although Chris Mack lost his side of the bet (no EUVL papers in 2011 SPIE AL), I still have to win my side of it, which called for HVM introduction by the end of this year. If EUVL is used this year to start developing a product that eventually sells in the marketplace, I will consider myself the winner. As TSMC is the only one who is officially moving this year into HVM, let us see how their development unfolds.

Most interesting word uttered in the conference: lagniappe (pronounced LAN-yap). Charlie Tarrio of NIST used it to describe an unexpected benefit in the alignment of his EUV reflectometer for measurements of reflectivity on a collector, which was bit larger than allowed in his chamber.

Most interesting Acronym: LOVE, for local overlay error budget, used by ASML to describe their model for improving machine to machine overlay.

Uncalled for comments on EUVL by someone in media: still tasteless and unprintable.

Knee-jerk reaction: a 5% drop in ASML stock on reports of damage to a CO2 laser at TSMC due to misalignment (which took two weeks to repair, as it is an installation and service issue and not a technical challenge).

Surprising paper: Final presentation  of the conference by Tagawa-san of the University of Osaka, showing that by using his “EUVL sensitizing chemical” combined with UV flood exposure, EUV and EB resist dose requirements can be drastically reduced. He showed an example of an 8.8 x increase in the sensitivity for EB resist for 75 nm L/S. I believe we should investigate what this approach can do for us in EUVL.

Most Progress: In the low dosage requirements of new metal based EUV resists. If we can go from 15 mJ to 1.5 mJ (Cornell’s results), we will need 10 x less source power. I can drink to that!

My Wish:  For EUVL to become a workhorse in our fabs by 2017, just like my van with the EUVL license plate has been at my household for many years now.

Is the Chip Industry as Important as We Think? Depends on Whom You Ask

Vivek Bakshi, EUV Litho, Inc.

For me, 2014 started with a focus on moving into my new office on my ranch that will allow me to do more higher-quality, uninterrupted work. After I finally finished moving in, I sat down to catch my breath and to contemplate the world I work in. Immediately these questions popped up:

Are we as leading-edge industry making a difference in the world?

Are my efforts to promote EUVL and help its transition into fabs making a positive difference?

Are we as scientists and technologists making the world a better place?”

This is not the first time I have pondered these questions. Not long ago, I responded with the following logic:

  1. The world as we know it cannot continue to exist without the latest computer chips. Taking away all the leading-edge chips would set humanity back faster than almost anything else.
  2.  Lithography is the main driver for producing leading-edge computer chips.
  3. I work on developing advanced lithography techniques – especially the most critical issue, EUV sources – so my work has to be important!
  4.  Our industry is the bedrock on which the new civilization stands.

Unfortunately, not everyone recognizes this. I shared my view with a friend who had just returned to Austin after many years in Hollywood. It turned out he took all the new and better chip-driven gadgets for granted. Yes, we use computers, he said, but all industries think highly of themselves. He told me Hollywood thinks it drives the world. Since then I have talked to more people and have gotten similar feedback: we get better gadgets every year and expect to pay less for them every Christmas. Business as usual, they say.

Still, I can’t help thinking that we’re special. Our leading-edge chip industry is driven by innovation and competition and not by regulation. Do you ever hear Congress debating legislation to make 14 nm node technologies available in 2014 so we can have faster computers for the next-generation X-box or IPad?  Not a chance! Instead, our industry self-innovates by trying to outdo our competitors. Our only price and performance guidelines come from competition– we deliver better products every year at lower cost, as driven by Moore’s Law and consumer demand. Which other industry does this?

However, when we read media coverage about the leading-edge chip business, much of it circles around the extension of Moore’s Law, when and if it will end, EUVL delays, source power, when we are going to have EUVL ready, etc.  That is the end of the story. So how as an industry have we ended up here?

First of all, we are here because of how the chip industry conducts business. By trying to move to EUVL as next-generation lithography, we are changing more than one thing in the critical technology of lithography, which is very difficult to do and hence the delay. The current light sources are plasma-based and what industry has achieved for EUV sources is phenomenal. However, making high temperature devices (35K or more) for 24 x 7 operation is extremely difficult and we still have a way to go. To make faster progress, we need larger knowledge and innovation bases in research labs around the world, and we do not have them.  Our industry now has at least half a dozen consortia, which are supposed to be working to generate a knowledge base to support solutions for difficult problems, such as those EUVL is facing today. However, their main focus has been on supporting suppliers in tool development, an important task to be sure – but no support has been given to EUV source research for a very long time, which is our number one issue. Last year major chip makers announced R&D support for EUVL via their investments, but did it go toward our number one issue of high power and metrology EUV sources? Work in other areas of EUVL is good, but sources are where we can expect the most benefit from R&D.

The second reason is how we share information in this industry. It is done by press releases, investor statements and mostly in formal large conferences – too large for any discussions or format to allow discussion or questioning of critical data. After many technical conferences, the presentations are not available for a while (if at all) or may appear in formal papers after a long time. This is why I organize biannual EUVL workshops that are small, allow discussions on the data provided, and make presentations available to all at no cost just a few days after the meetings end.

The third reason is the type of OEMs we have in our business. Some are leaders and risk-takers and as a result they win big and grow, like ASML. They “bet the farm” on EUVL and it is paying off for them. In the near future, there will be only one leading supplier for critical litho tools – ASML. As I say for any business, there are three critical elements – investment, core competency and risk. Some suppliers are not willing to take risks or make investments, but I believe that many lack the core competency for getting into EUVL as well. You can acquire knowhow by buyout, but not always. ASML via its network of R&D institutes and sub-suppliers has built a vast network of competency that has supported its EUVL tool development. Such networks are not built in years, but over a decade.

History Repeats Itself – Rescuing Moore’s Law

I would like to focus on the topic of light sources for lithography, which is of interest to many. If we look at the history of chip-making, we find that in the beginning of the current deep ultraviolet (DUV) based processing, around 1980, in order to stay on Moore’s Law, IBM wanted to move to shorter wavelengths. At that time there was also a shortage of photons in shorter ultraviolet light, as we are seeing in the industry’s transition to 13.5nm wavelength to stay on Moore’s Law. Then Grant Willson and his colleague discovered chemically amplified resist, which allowed us to do more with fewer photons. We are at a similar place today: while many are looking for more photons, the solution may come not from that direction (higher source power) but from being able to do more with the photons we have.  I believe that Prof. Willson and his team, or someone else of that caliber, will once again come to rescue Moore’s Law by showing us how to do more with less. I hope our industry is exploring this option well.

Nobel Prize and Computer Chip Industry

Coming back to the perception of our industry, let’s talk about the Nobel prizes that have been given in chip-making. Although our industry can boast of a few Nobel prizes, there are not enough, considering its history of innovation and its contributions. Three have been awarded over the past 50 years – a 2000 Nobel prize in Physics to Jack S. Kilby for his part in the invention of the integrated circuit, a 1973 Nobel Prize in Physics to Leo Esaki and Ivar Giaever for their experimental discoveries regarding tunneling phenomena in semiconductors and superconductors, respectively, and a 1956 Nobel in Physics to William Bradford Shockley, John Bardeen and Walter Houser Brattain for their research in semiconductors and their discovery of the transistor effect. I certainly hope that there will be more in coming years.

Prof. Willson’s discovery of chemically amplified resist (CAR) has revolutionized modern computer chip-making. It stands among great discoveries and its implications have been vast – any leading-edge electronic device that you touch (IPhone or Kindle or laptop) has been made possible due to processing based using CAR – his invention. For what others inventions we can say this? For his work he has received many well deserved prizes, including the Japan Prize (similar to the Nobel) in 2013. I believe that his invention deserves recognition by the Nobel Committee for Chemistry. I certainly hope that leaders of our industry will write a recommendation for him to the Nobel Committee and share with us on the role of his invention and contributions. I will be happy to publish them in this blog.

Source Workshop Presents Data on Readiness of 50 W EUV Sources to Support EUVL Scanners

Vivek Bakshi, EUV Litho, Inc.


The 2013 Source Workshop (Nov 3-7, 2013, Dublin, Ireland) brought together one of the world’s largest annual gatherings of EUV source experts. I will focus on highlights of the workshop in this review.

In his keynote talk, Vadim Banine of ASML reminded the audience of the advantages of EUVL over double and quadruple patterning. He said that 50 W EUV sources have now demonstrated good dose control and are now available for deployment in the field.  (ASML earlier this year acquired Cymer, a maker of high-power EUV Sources.) ASML also presented data on the feasibility of source power of 175 W at the first focus (720 W at source), and utilizing new, protective cap layers to give collectors six months of life.

Gigaphoton, the only other supplier of high power EUV sources, presented results of their development efforts. Although their source power is only 15 W with 2.5 % conversion efficiency (CE), their Sn laser produced plasma (LPP) technology has some key advantages for power scaling: dual wavelength pre-pulse, magnetic mitigation of debris and IR reduction technology for collectors, which they have developed with Rigaku. Collector rejection of IR radiation (10 µm from lasers) works with only 10% loss of reflectivity of collectors. Gigaphoton also showed that picosecond prepulse improves CE and reduces mists. High power lasers remain the drivers for source power scaling for ASML and Gigaphoton, and Gigaphoton is working with Mitsubishi on transverse flow CO2 laser development and on an axial flow CO2 laser development with Trumpf.

Mark Phillips of Intel in his keynote talk offered a balanced criticism of progress in EUV source technology. He said that 40-80 W of stable sources with master oscillator power amplifier (MOPA) technology and prepulse, linked to production level EUVL scanners (NXE 3300B), are needed to reestablish confidence in EUVL and process development. He expects these power levels to be available in the first half of next year, in keeping with the timeline of HVM insertion in 2017 by his company.

As Intel now expects that a pellicle will be needed for EUVL scanners, this position will help resolve the issue of choosing of actinic vs. e-beam technology for mask defect inspection, as only photon-based inspections can be used with a pellicle. This will hopefully result in an increased engagement between metrology source suppliers and mask defect inspection tool makers. Various makers of EUV sources for metrology application presented the performance of their sources, including Adlyte, Energetiq, Naextstream and NewLambda technologies. In an interesting paper, Serguei Kalmykov of Ioffe Institute, Russia demonstrated a 30-60 % increase in CE of Xe LPP sources via application of pre-pulse technology.

In other interesting results:

V. M. Krivtsun of RnD-ISAN /EUV Labs presented the concept of power scaling via increase of pulse energy, instead of the current option of pulse frequency for power scaling. His group also demonstrated a closed tin system with tin jets at velocity of 5-15 m/s (max temperature of 350 C), with potential for power scaling for Sn LPP sources.

In another invited paper, Alexey Lopatin of the Institute for Physics, Russia presented his design of freestanding film elements for use as pellicles in an EUVL scanner. These films of merely 20 µm thickness have 84% transmission for EUV wavelength.

In the keynote on November 6th, Margaret Murnane, University of Colorado, Boulder, talked about coherent X-Rays from tabletop femtosecond lasers for applications in nanometrology. She discussed the ability to take high harmonic generation into the keV region and potential metrology applications in the Zepto (1E-21) and Yocto (1E-24) second physics!

Many excellent papers on multi-layer optics, modeling, BEUV, XUV sources and XUV Application were presented in the workshop and can be downloaded at the workshop’s website at

Advancing EUV Source Technology – 2013 Source Workshop (November 3-7, 2013, Dublin, Ireland)

By Vivek Bakshi

A lot of effort goes into enabling EUV sources for EUVL scanners and mask defect metrology tools to ensure they meet the requirements for production level tools. Researchers and suppliers around the world have been working on many issues to ensure their availability.

Challenges include modeling of sources, improvement of conversion efficiency, finding ways to increase source brightness, spectral purity filter development and contamination control. These and other issues are among topics that were proposed by a technical working group for the 2013 Source Workshop in Dublin, Ireland. A detailed list of topics is available at this link.

This workshop also will invite experts on XUV and BEUV sources, as learning and applications in those areas are very relevant to EUV sources. Due to lack of funding in the EUV source area and the emerging XUV market, many source experts are now also working in XUV sources.

Now in its fourth year, the annual Source Workshop is the industry’s largest gathering of source experts. This year’s keynote talks are from ASML, Intel and University of Colorado, Boulder. The agenda can be found here and abstracts can be found at this link.

Abstracts for post-deadline poster papers will be accepted until October 15, 2013 at I will share the highlights of the Workshop on this blog in mid-November.


Still a Tale of Two Paths: Highlights of Lithography Panel from SEMICON West 2013


This year, I moderated the industry’s Lithography Panel during SEMICON West 2013 to a standing room only crowd. This interest in Litho was not a surprise as Litho is the key enabler of Moore’s Law.

Currently, both 193 immersion multiple patterning (193i MP) and EUV Lithography (EUVL) are the leading contenders for next generation lithography for the 10 nm node and below. The SEMICON West 2013 panel was great as we had speakers on both 193i MP (Nikon and Synopsys) as well as EUVL (SEMATECH and ASML). TEL talked about directed self assembly (DSA) applicable to both approaches. Nowadays all large workshops and symposia have separate tracks that focus on one or the other, so it was good to have both of them together. The title of the lithography panel was “Still a Tale of Two Paths” and both sides essentially talked about the merits of their own approach and issues with the other’s approach. (ASML makes both EUVL and 193i scanners while Nikon makes only 193i scanners. Synopsys supports both approaches via their modeling software and TEL makes tracks for both types of scanners.)

The lithography session underscored the issues that we are having in the search for next generation lithography (NGL) technology. There were “two elephants” in the room that all speakers tried to ignore: 1) the cost, complexity and possible technical impossibility of 193i MP below 10 nm, and 2) delays for EUVL due to lack of source power.  The “elephants” were not discussed but their presences were very much felt. 193i MP is getting very expensive and complicated and may not be able to support patterning below the 10 nm node without additional complexity that chipmakers are not willing to adopt. EUV lithography right now still remains in the pilot line due to lack of adequate power. Hence, if scaling required by Moore’s Law is no longer supported soon, there will be an historic cost increase. Before I give my opinion on what I think may happen, let me first summarize what I heard from speakers and otherwise at SEMICON West 2013.

Talk Summary

Nikon titled its first talk “EUV Revolution Has Been Postponed” and then described how to move forward with 193i MP. It is the most probable route if EUVL is absent in HVM to provide resolution scaling, control of CD uniformity and overlay, and flexibility with design and cost. However, it is known that flexibility is reduced in MP with design restrictions and I pointed out during Q & A that Nikon’s comparison of MP with EUVL was not correct. The cost for 193i MP must include all equipment needed to support this technique. A scanner in MP is not just a scanner but a “large composite tool” that contains tools for deposition, etch, ash and metrology, and cost of all these must be included. However, in the absence of EUVL in HVM, 193i MP remains the main choice for chip makers.

In the next talk, Stefan Wurm of SEMATECH pointed out the readiness of EUV resists for EUVL introduction. EUV resists have been ready in part due to the testing infrastructure provided by SEMATECH and other consortia. His consortium is now focused on getting EUV mask blanks ready for HVM introduction of EUVL. The next set of challenges is to reduce pits, bumps and scratches in the substrate, focus on mask lifetime issues during cleaning and handling and reduce damage of backside coatings. In response to a question, Stefan pointed out that an EUVL mask should be able to go through 100 clean cycles, compared to today’s performance of 30 to 40 cleans.

Skip Miller of ASML presented data on the progress of EUVL scanners. He reported the shipment of two NXE3300B scanners to customers. He pointed out 30-70 percent lower cycle time via EUVL scanners compared to 193i based scanners and a large process window for 14nm node and below. He also pointed out that at 10nm node EUVL allows 50 percent scaling, while only 25 percent is possible with 193i MP. Even for grided SRAM chip makers will prefer EUVL, as limited overlay makes MP very difficult. For NXE3300B, throughput targets are 50-125 WPH, based on indications that his power vs. throughput curve will correspond to 68 – 250 W of source power. Currently 40-50 W of sources have been run with good dose repeatability of <0.5 percent for total run time of 20 hours, consisting of many hourly runs. I am not sure if runs were at 100% duty cycle. The target for these scanners in 2014 is for 70 WPH, and he expects 250 W source power to be achieved in 2015.  

Mike Rieger of Synopsys described the role of electronic design automation (EDA) in enabling scaling via 193i MP. Scaling is possible without EUVL but will entail increasing cost, process complexity and design rules restriction. He pointed out need to keep cost under control for these options.

Ben Rathsack of TEL presented collaborations in the area of directed self-assembling (DSA), an emerging technology area that can help 193i MP as well as EUVL. He described his collaboration efforts in the area of defect reduction metrology via continued research with universities and consortia as well as chip makers.

The EUV revolution has not been postponed – it is delayed. The advantages of EUVL due to relaxed k1 and cost competitiveness are well known to chipmakers and what they want are tools that can support HVM, and those are delayed due to low source power.

Industry’s Position and Critical Questions

“Lithography is one of the highest priorities of our industry” and “EUVL must happen” were some of the comments we heard from consortia leaders at SEMICON West in other panel discussions in the meeting. These industry consortia have a combined budget of few hundred million per year and most of it is focused on EUVL. They have done a wonderful job of supporting mask and resist research. As they are funded by chipmakers and some government support, one can assume the view of the consortia is the position of chipmakers as well.

“Suppliers will deliver the EUV sources” has long been repeated by all consortia and they reiterated their position in this meeting as well.  Currently consortia support all but EUV source projects, while EUVL continues to slip due to lack of adequate source power. In the end it is the chip makers who pay for the delay and the consortia reflect their strategy, so one wonders why this is so. Perhaps human psychology it is at work here. People do what they are comfortable doing and generally avoid trying new things unless calamity strikes. Mask and resist is something chip makers know how to deal with and have experience in developing these technologies. However, they do not have a team of plasma experts or source experts to guide them. Neither do consortia, so one has to go with what suppliers can provide. It is interesting that we are ready to bet the future of Moore’s Law rather than do something to hedge our risk. Year after year source power roadmaps slip, but no additional action is taken except to wait for new supplier source power roadmaps that we know will slip again.

Some point out to me is that the critical question today for the industry is, “If EUV Sources will be ready, will mask infrastructure be ready?” I agree that this is an important point and will address it below briefly. However, I think the most important question is, “What we will do with ready EUVL masks and EUV resists, if sources delay EUVL sufficiently to push it out further on roadmaps?”

EUVL mask infrastructure challenges (as detailed in the 2013 EUVL Workshop by Intel, Toshiba and GlobalFoundries) are certainly very difficult but do not look like showstoppers. They can be addressed with significant efforts and investment. What is lacking in the mask area is the consensus on key topics such as choice for masks for High NA tools, need for pellicles, how to inspect patterned masks during manufacturing, and need for various mask metrology tools during manufacturing, usage and maintenance of masks. Mask defect metrology tools are still not ready mostly due to lack of high brightness (not high power) EUV sources. In the upcoming 2013 Source Workshop, I expect more discussions and ideas presented on how to advance source technology for metrology sources.

My Predictions

I may be biased toward EUVL, but 193i MP will get more expensive and complex than EUVL at every next node, but EUVL is not yet ready so chip makers have no choice but to go with what is available. ASML announced in their presentation that two NXE3300B tools have been shipped and nine more are on their way to chipmakers. I think 50 W sources will be ready and working in NXE3300B sometime in 2014, corresponding to 43 WPH throughput. 100 W sources will be ready in 2015 or 2016 corresponding to 73 WPH. The readiness of 250 W EUV sources cannot be safely predicted, unless we see 100 W sources ready and have identified the issues to ensure that they are no showstoppers. I am not convinced that present approaches can get to 500 W sources. It is easy to put them on roadmaps, but delivering them is another question.

With 73 WPH, one can start with EUVL in HVM, as that cost is going to be better than for multiple pattering. Below 10nm nodes, the cost for 193i MP is high due to 4x or 8x patterning and for EUVL due to lower throughput due to low source power. I am not as concerned about 450mm transition for EUVL tools. EUV sources will have to deliver 2.5 x source power to keep the same throughput as 300mm tools, and that does not seem to be out of question by 2018, when the competition will be 4x patterning with extreme design rule limitation.

Another question to ask is how far you can scale with 193i MP and what are the cost implications. If EUVL is still not ready in few years and 193i MP is not feasible due to cost and complexity, what do we do? Both are projection lithography and rate of transfer of information from mask to wafer cannot be beaten by direct write techniques? This topic needs continued discussion.


Getting out of SEMICON for my next meeting, I was stopped by a colleague, who reminded me that EUVL was dead. Of course, he has been telling me the same thing since 2006, even while his own NGL approaches have gone bust. It appears that industry has been split into pro- and anti-EUVL camps for some time. It is becoming something like a religious war and there is less of a dialogue between these two camps. EUVL has been proven to be capable but it is delayed and will not be ready for HVM for a few more years. 193i MP is getting to be very complicated and expensive so chip makers have to have a backup, and that is EUVL. In the end it may be a mix of EUVL and 193i MP that will enable continuation of feature size scaling. The industry must continue to follow Moore’s Law and will do whatever it takes to keep up the scaling, so NGL will remain a hot topic for many years to come.

“Taming of Pele – the Fire Goddess”: 2013 EUVL Workshop Highlights

Keynote talks

The sixth EUVL workshop was held June 11, 14 in Maui, HI with participants from the US, Korea, Taiwan, Japan, Europe and China.

The first keynote talk was delivered by Sam Sivakumar, who is leading the EUVL pilot line for Intel Corporation. He showed the yield data from his EUVL pilot line, obtained since his SPIE Advanced Lithography symposium presentation, that lead him to believe that there appears to be no fundamental roadblock to EUV achieving yield parity with 193i;  any qualifying issues, he said, are not related to EUVL.  In Sivakumar’s opinion, we must make progress on key issues of source power and mask defectivity in the next 1- 1.5 years. Although power delivery is getting better for the ASML’s NXE3100 scanner being used in his fab, source power remains the main impediment to EUVL being placed in HVM.

Tatsuhiko Higashiki (Toshiba) in the second keynote talk emphasized that at nodes 1x nm and below, non EUVL choices are not only unattractive – they are, in fact, scary!  EUVL remains the only alternative, supplemented by double patterning (DP) and directed self-assembly (DSA). He also cautioned that in comparing EUVL to other lithography options, one needs to think about not only cost but also cycle time – something many comparisons do not do include in their cost of ownership calculations, even though increased cycle time is inherent in double patterning techniques and adds significant cost to that technology.

Panel Discussion: EUVL Readiness and Insertion Timeline

Following the keynote talks, panelists gave their opinions on what will be available to support lithography in the near future and related challenges. Sivakumar pointed out that EUV is currently targeted as the primary option for the 7nm node (2015 development, 2017 high volume manufacturing [HVM]) by Intel.

Sushil Padiyar of Applied Materials (AMAT) pointed out for the 12- 8nm nodes, choices are 13.5nm with double patterning (DP), 13.5 nm with hyper NA, or going with 6.x nm.  The 13.5nm with DP option seems to be the best candidate, as its feasibility has been already demonstrated.  The best guesses for 5-7nm are EUV with self aligned DP, and a combination of 193i multi-patterning and EUV. He pointed out the current positional accuracy for DSA is ~ 3nm, so the 193i /EUV combination will most probably need to be teamed with a self aligned (SA) process.

Tatsuhiko Higashiki (Toshiba) said that the semiconductor business will mature if lithography and mask cost reduction is not achieved. He believes that 9 inch masks are preferred by memory makers and EUV and DSA combinations will be the leading choices for lithography in the future.

Pawitter Mangat of GlobalFoundries pointed out the urgent need for EUVL readiness in the next two years. In his opinion, the industry needs to decide soon on masks for high NA scanners due to long lead times for developing this technology.

In a survey distributed to workshop attendees on EUVL readiness and technical challenges, most respondents predicted HVM insertion in the 2015-17 timeframe. Source power, mask defect and pellicle readiness were considered to be the leading challenges.

Workshop highlights

Workshop presentations focused on R&D topics, with the following highlights:

Greg Denbeaux of the University at Albany described his experimental design to study electron chemistry of secondary electrons. This setup will allow direct measurement of electron penetration depth and direct measurement of electron blur. Results will be used to improve resist modeling software to enhance our understanding of the functioning of EUV resists.

Grace Ho of NUK University, Taiwan described “Outgassing, Photoablation and Photoionization of Organic Materials by the Electron-impact and Photon-impact Methods.” The question of equivalence of resist outgas testing via electron beam vs. EUV photons is still not fully answered and in some cases, per her work, one can get different outgassing results for these two methods. As the basic physics of these two processes is different, this is not a surprise. As e-beam testing is frequently conducted to qualify new EUV resists, this topic needs to be continued to be evaluated to ensure the accuracy of assessments.

Cameron Moore of XEI Scientific described damage to various EUV specific materials under plasma cleaning. As dry plasma cleaning shows advantages over wet cleaning of EUV related contamination due to reduced damage to EUV components, we need to understand the effects of plasma cleaning on various vacuum components as well.

Yuriy Platonov of RIT described results of normal incidence collector optics for laser produced plasma (LPP) with average collector reflectivity of 54.3 percent. He also reported that for his Illuminator optics, the central wavelength is within +/-0.8 percent for all five optics sets. For collector refurbishment, he has demonstrated loss of only ~1 percent after two refurbishment cycles. Increased collector reflectivity and stable central wavelength is essential for increasing EUVL scanner throughput. Moving forward, we can see an increased demand for refurbication of normal incidence collectors for Sn Laser produced plasma (LPP) sources, so these were important results.

The meeting included six representatives from China, reflecting that nation’s increasing efforts in EUVL R&D. Prof. Yanqiu Li of Beijing Institute of Technology showed her modeling efforts for 0.3 NA EUVL scanners.

Performance of Cymer sources was presented in the US region review by Greg Denbeaux of U Albany. Sn LPP source now has power of 50 W with 0.5 percent stability for master oscillator power amplifier (MOPA) operation with prepulse. These results were from several continuous one-hour runs, and operation time is expected to rise soon. Denbeaux also presented results from SEMATECH and CXRO, among others, actively involved in EUVL related research. Overall, six EUVL regional overviews were presented from the US, Europe, Taiwan, China, Korea and Japan, demonstrating strong commitment in development of EUVL infrastructure and R&D. However, R&D for the most critical issue of HVM sources is still mostly absent due to lack of funding.

Padraig Dunne of University College Dublin (UCD) pointed out that 6.x nm emission from gallium (Ga), which is a liquid at 30° C, and germanium (Ge) is possible with electron temperature of 50-60 eV. This is significant as 110 eV plasma is needed for gadolinium (Gd), a material currently being considered for light sources for 6.x nm based lithography.  As the temperature of Ge plasma is less than that of Gd plasma, it will take less laser power for Ge based 6.x nm sources. In addition, he suspects that conversion efficiency (CE) may be greater for Ga and Ge plasma than that for Gd.

Akira Sasaki of JAEA pointed out that Sn mist targets, an alternative tin delivery system being currently considered for Sn LPP sources, will require new modeling techniques and shared initial results of his modeling. Modeling work is certainly needed to ensure that maximum benefit for CE increase is obtained with this new method.

Energetiq, ETH Zurich (together with their spin-off company, Adlyte) and NewLambda shared their continued efforts on development of metrology sources for supporting mask defect detection metrology tools. Currently, Energetiq’s sources are used in the first generation of mask defect metrology tools under development.  ETH Zurich has started a new facility (ALPS II) for further development of their metrology sources.

Addressing the topic of Mask infrastructure readiness, Pawitter Mangat of GlobalFoundries pointed out that zero defect printability is not same as zero defectivity on masks. He presented an excellent summary of mask challenges, actions needed to address them and new opportunities of thinner absorber and pellicle development.

Hiroto Kudo of Kansai University described molecular resists based on Noria derivatives (Oligomer derivatives) for EUV resists. A smaller line edge roughness (LER) as compared to current resists is expected in future through use of these polymers.

Yoshi Hishiro, JSR Micro Inc., shared a wide variety of improvements achieved by his company in EUV resists for 16nm node. One example is LER improvement via shorter acid diffusion length and development of EUV topcoat to remove out of band radiation (OOB). As OOB increases LER of printed features from 4.6 to 6.8nm, topcoat was able to bring LER down to 5.0nm.  He showed that firm rinse reduces pattern collapse and decreases LER by 15 percent. In the results on use of DSA, an EUV+DSA approach allowed an increase in sensitivity of resist and improved the CD uniformity (CDU) of patterning, resulting in 14nm line and spaces (L/S) and 18nm contact holes (CH).

Takahiro Kozawa of Osaka University gave an excellent talk on stochastic effects in chemically amplified resists for EUVL. In his study, he determined that  the amount of chemical reaction required at 16nm half-pitch (HP) increases by 74 percent compared to 60nm HP, and the optimum diffusion length for 16nm L/S pattern is ~ 10nm.  Such fundamental work provides insight into the working of EUVL resists will enable development of newer resists to reduce LWR.

Take Watanabe of Hyogo University presented his analysis using synchrotron radiation  (SR) based absorption spectroscopy for the chemical reaction analysis for EUV resist to explain the difference in resist sensitivity of various EUV resists from increase the acid yield.

Sushil Padiyar of AMAT presented results of 9nm CH and 8nm L/S via EUV DP. This work emphasizes the role of DP in the extension of EUVL.


The workshop attendees voted to award Best Oral Paper to Prof. Takeo Watanabe of Hyogo University for his invited presentation, “Recent Activities of the Actinic Mask Inspection using the EUV Microscope at Center for EUVL.

The audience also posted decisions for the best poster papers, with these awards limited to students this year. First place went to SeongChul Hong of Hanyang University, South Korea for his paper titled, “Attenuated PSM for mitigating PSN effect in EUVL.” He is a graduate student of Prof.  Jinho Ahn.  

Second place poster award was given to Hung-M. Lin of NUK, Taiwan for her paper, “Quantitative Outgassing Study of Photosensitive Films upon Irradiation at 13.5 and 6.7nm.” She is a graduate student of Prof. Grace Ho.


EUV source power is showing progress but remains the main issue for HVM insertion. Without innovations, progress in this critical area may remain slow. Intel plans pilots in 2015 and 2017 HVM at the 7 nm node. Mask issues still require industry coordination, but the industry can be expected to address them with significant efforts. EUV DP, maybe with help from DSA, seems to be the choice for going below 10nm node and remains preferred by chip makers over 193nm immersion multipattern based approaches. EUV Resist is showing good progress.

Prologue – Taming of Pele – the Fire Goddess

Looking at the history of optical projection lithography, it appears we have learned how to manipulate photons well but not how to generate them effectively from hot plasmas for plasma machines that can operate 24 x 7 at a power level that we need in factories. We do not know if we can support the levels of power that we will need in the near future via our current approach. We need new ideas and we need to think out of the box to improve current technology and identify strong alternative candidates. It comes down to learning more about the taming of hot plasma.

In Maui, site of the EUVL Workshop, there are stories about the taming of Pele – mythical goddess of fire – who with burning lava (the geological version of hot plasma) created the islands of Hawai’i, with controlling force delivered by the surrounding sea. Hawaiian poetry also tells us that the the same force also tamed her:

Huaka’i ihola ‘o Pelehonuamea i ke kai Ko’olau

ma’e’ele ‘o Pele i ke kai kapu o Kamohoali’l

Pele, who gave birth to the reddish earth, flows like the ocean to Ko’olau

But she is benumbed by Kamohoali’I’s sacred seas.

[Hawaiian poetry and translation taken from Na Wahi Kapu o, a beautiful book of photographs of  Maui and poetry by Kapulani Landgraf, Native Books, 2003.]

As we lithographers struggle to transform hot tin plasmas into useful servants that will help us print circuits night and day, let us be guided by the tenacity of the Hawaiian seas, which tamed the seemingly uncontrollable energies of Pele herself!