Author Archives: sdavis

New Frontiers for EUVL – Sources and Metrology: Topics for 2017 Source Workshop (November 6-8, 2017, Dublin, Ireland)

By Vivek Bakshi, EUV Litho, Inc.

As the focus of industry and press turns to insertion dates for EUVL in fabs, I am putting my thoughts on future nodes of EUVL for several reasons. First, I see EUVL in high volume manufacturing (HVM) fabs as a done deal, with insertion starting in HVM next year. The insertion dates by leading chip makers will be somewhat staggered because of their existing plans and products, specific insertion criterion, and so on. So there is not too much news in whoever announces using EUVL in a production line a quarter or two before the others. Second, we are approaching the phase of Moore’s Law where we face some difficult challenges in extending roadmaps to 3 nm and beyond. EUVL is in the forefront, but challenges are all around. For EUVL to succeed at these nodes, we need to focus on several technical areas. These areas are ripe for R&D, and successful solutions will lead to new and improved products for those who pay attention and invest. In this blog, I will focus on EUV Sources that will enable not only EUVL scanners but also leading-edge metrology needed for EUVL at 7 nm nodes and beyond. I will highlight how several papers in the upcoming EUV Source Workshop in Dublin (November 6-8, 2017) will address these topics.

High Power HVM Sources             

Industry has decided on Sn laser produced plasma (LPP) as the technology of choice, which uses tin droplets as an energy convertor for CO2 lasers. 250 W is already here, with development in progress for 500 W sources. As we look forward to higher powers of 500 W and beyond, there are a good many challenges than require serious R&D efforts. Current conversion efficiency (CE) is 5%, with 8-9% possible. It is not so easy to get that extra increase in CE, but the benefit is enormous in terms of the need for lower CO2 power (higher scaling), more stable sources (less overhead) and less debris (longer collector and component lifetime). Each of these items is critical, and to work on them we must look closely at fundamental data for Sn, and learn more via modeling and experiments how tin converts from liquid to plasma that generates EUV, while generating debris in the process. How far we can scale plasma sources beyond 500 W is still not known. If we need 1000 W, do we do this with plasma sources or free electron laser (FEL)? We may need to move beyond droplet generated sources for Sn LPP for higher powers, and FEL proposals need further evaluations.

In the source workshop this year, we will have sessions on fundamental data, modeling and high-power sources, which provide insight on these topics. There will be papers from ARCNL, DIFFER, LANL, LLNL, Max Plank Institute, University of Tokyo and many others. We also will have updates on high power source performance from ASML and Gigaphoton.

Broad-band EUV Sources for Wafer Inspection

This is a new topic that has seen much interest recently. As actinic patterned mask inspection tools are not ready, chip makers must rely on wafer inspection to identify mask defects. Current 193 nm based technologies have their limitations in terms of extending to 7 nm and beyond, and we need to reduce the wavelength of inspection tools. A study by NIST has showed that 47 nm (and not 13 nm) is the wavelength of choice for wafer inspection at future nodes. There are several candidates for such sources, and current learnings from EUV plasma source development and its integration can be applied to these broadband sources. I was asked by the source workshop’s committee last year to come up with draft requirements for such sources so that source suppliers have more guidance. So we plan to present a draft proposal for requirements for such sources. KLA-Tencor, Energetiq and ISTEQ plan to present the status of their plasma based broadband EUV sources, which can be applied for wafer inspection. I see another version of EUV sources emerging to help extend the Moore’s Law, by supporting advanced metrology.

Lasers for EUV Source and Metrology

Last week, one of my colleagues alerted me to recent development of 46.9 nm lasers which may be applied for wafer inspection. These lasers have only a fraction of mW of power, but after seeing how well 13.5 nm high harmonic generation (HHG) based inspection prototype tools have done, I believe one ought to review these lasers in the context of wafer inspection. The source workshop also will be covering the latest on HHG lasers and their applications, which continue to be explored as an alternative to actinic aerial image metrology systems (AIMS) and potentially for other mask defect applications. In a 2017 EUVL workshop paper, Prof. Murnane showed how HHG based actinic inspection can do a good job of defect review, and we already know that Samsung is using this technology for their EUVL development. I believe that this technology can be scaled to cover patterned mask defect inspection (PMI) as well, at least for a stopgap basis, while industry works on PMI tools.

One of the other ways lasers help Sn LPP EUV sources are in terms of pre-pulse. Pre-pulse shapes the tin droplet to a larger size, which increases coupling with the CO2 laser and increases source CE. Gigaphoton uses neodymium doped yttrium aluminum garnet (Nd:YAG) lasers with picosecond pulses, while Cymer uses a wavelength from the CO2 laser itself. YAG lasers have their own advantage and it is no small task to develop 500 W ps YAG lasers for per-pulsing. We will have updates from Trumpf and HiLase on their programs to develop these ps pre-pulse lasers, which also may play a role in FEL based EUV sources.

Metrology Sources- Plasma based and beyond

Metrology sources at 13.5 nm will enable actinic patterned mask inspection. The current workhorse for industry is the source from Energetiq, and they need higher brightness for meeting HVM requirements. Many are working hard to meet the HVM metrology source requirements by plasma sources, and Ushio, ISTEQ, ETHZ and Fraunhofer will update us on the latest in their metrology sources.

What has me excited is a new concept beyond plasma. In the 2017 EUVL workshop, we heard about compact accelerator based sources that can potentially power a scanner. Now we have a proposal from PSI for a compact source for metrology that is also based on accelerator technology. I look forward to finding out more about this non-plasma based metrology source technology.

So I am looking forward to lots of exciting papers next month in the workshop that address leading edge EUVL topics, and I will report back in a future blog on what I learn at the workshop. Abstracts for these papers and the agenda for the workshop are available at www.euvlitho.com.

EUVL Technology Status Update

By Vivek Bakshi, EUV Litho, Inc.

This blog gives the latest update on the status of EUVL, based on data released this summer from the 2017 EUVL Workshop, 2017 Semicon West and recent announcements. This update is in the format that I previously introduced to simplify the vast amount of information from the 2017 SPIE AL EUVL Conference. It includes a short summary of EUVL Status, a list of notable updates since the 2017 SPIE AL meeting, and additions to the current list of EUVL Challenges at various nodes (complete list previously published on this site (List of challenges at 7, 5 and 3nm nodes). Another blog, “New Frontiers for EUVL – Sources and Metrology” will be published tomorrow on this site. 

  1. Current EUVL Status

 

Source: 250 W standalone source power has now been demonstrated at ASML (210 W in Q1 2017). Current power of integrated sources is at 148 W, corresponding to 104 wafers per hour (WPH) scanner throughput in-house at ASML. Stable 130 W power in scanner has been noted in field. In ASML lab, EUV source power is 375 W, in burst mode at 50 kHz. 200 W of stable power may be available in field in 2017 or early 2018. Source power is now meeting requirements for the introduction of NXE3400. Current source availability is at 75%, while high volume manufacturing (HVM) requirements are >90%. Lifetime of droplet generators and collectors are improving, but need further improvement to meet HVM requirements. Collector lifetime in 2016 was 1.5x better than the previous year. Reflectivity drop for collector is now 0.4% per gigapulse. Encouraging progress by Gigaphoton, a second supplier of high power HVM EUV sources. Options for EUV Sources beyond 500 W are under study. 

Scanners: Fourteen EUVL scanners are now in field. Four scanners were shipped in 2016. Specs are 0.3 nm critical dimension uniformity (CDU) and 1.8 nm overlay. For 148 W, scanners demonstrate 104 wafers per hour (WPH) throughput, with an increase of 8 wafers WPH achieved via increase of stage speed at the same source power. NXE 3300 scanner availability at >75%. The top contributor to scanner tool downtime is the exposure source.

Higher numerical aperture (NA) EUVL scanner design is now ready, with anamorphic optics (4x/8x magnification) for EUVL extension. Higher NA scanners will have smaller depth of focus (DOF) (1/3 of 0.33 NA tools), print half field – so will require stitching. Scanners will have requirements for a larger cleanroom. For defect inspection for mask for these tools, a higher resolution for actinic inspection for defect review (AIMS), mask blank inspection (MBI) and patterned mask inspection (PMI) tools will be needed.

Masks: Mask blank defects are acceptable for now via defect avoidance and repair. Mask defects > 60 nm are zero. Total defects >23 nm spherical equivalent volume diameter (SEVD) in low single digits, with actual number depending on mask pattern density. Compensation for 3D mask effects in the near term will be done using source mask optimizing (SMO) and in the longer term by using new materials for mask stacks.

Mask Pellicles: Mask defect addition during manufacturing is still a concern for chip makers. The unpredictability of adder events drives the need for pellicles. Pellicles can now withstand 140 W of source power and plans for cooling hardware are in place for a 205 W upgrade. Pellicles need to be ready for 250 W by 2H 2017. Current single pass transmission is 85%. Current fixed pellicle design needs to evolve to provide future solutions. New carbon nanotube based pellicles have been proposed from IMEC. Intel tested pellicles for >4 K wafers at 140 W with no added defects. This is a current topic of focus for readiness for HVM. 

Mask Defect Inspection: Need for AIMS, mask blank inspection (MBI) and PMI remains. Defect review is being addressed. Samsung has made its own AIMS tool for defect review and plans to use it for HVM. Tool is using a high harmonic generation (HHG) based EUV source and a scanning zone plate. Zeiss is now shipping its first AIMS tool. Actinic patterned mask inspection (APMI) tool is still missing, while MBI tools are ready for current needs. Mask defect inspection is being done via wafer inspection for now, but at a cost and with lower yield. APMI is the only red flag item for 7 nm insertion of EUVL. We need APMI for pelliclized masks.

Resist: Adequate for 7 nm node but better local CD uniformity (LCDU) required for future nodes. To address stochastics, we need increased EUV dose and increased EUV absorption of resists. EUV resists with smaller reactive volume, more uniform distribution of components, fewer components and higher dissolution contrast are needed. Lots of talk about stochastics, but I believe it will be addressed and it is not a showstopper, although it will need a good bit of work. It is important to note that resist image is only an intermediate step, and there are still several knobs available to improve the image and performance of the final circuit – which is what matters.

Need to understand the interaction of EUV radiation with resist and design resist materials for addressing stochastics. Need to address new challenge of micro-bridging (also called nano-bridging). Its relationship to dose, type of resist and linewidth roughness (LWR) is not clear. Optical proximity correction (OPC) and Litho-etch optimization may help reduce this effect.

Continued work on chemically amplified resists (CAR), metal based inorganic resists and molecular resists to support 7 nm and beyond. Out of band (OOB) filter is now in scanner that also acts to keep out resist outgassing products.

 

  1. Notable Updates (Since 2017 SPIE AL Meeting)

 

Scanner and imaging

  • >1 M wafers exposed on NXE 33x0B in fabs.
  • Meeting 5 nm logic requirements with 0.3 nm CD uniformity (CDU) (13 nm L/S) with LWR at 3.8 nm (34 mJ) and 3.2 (58 mJ).
  • Now imaging 20 nm contact holes (CH) with CDU of 1.2 nm.
  • Demonstrating clear benefit in terms of illumination for NXE3400 over NXE3300.
  • NXT to NXT matched overlay is now 1.8 nm.
  • Throughput of 104 WPH for 148 W source for NXE:3400B (at ASML – Q1 2017)
  • Faster wafer swap, transmission improvement and source power increase will enable 125 WPH.
  • Zero adders during scanner operation, with light on, for 2400 wafer exposure demonstrated.
  • Larger NA (0.55) scanner will result in reduces dose requirements and higher effective throughput (as fewer LE steps will be required).
  • High NA will also help mitigate LCDU.
  • Infrastructure already in construction at ASML and Zeiss for high NA EUVL scanners.

 

Source

  • 250 W demonstrated at ASML.
  • CE is now at 5.7% at ASML.
  • >700 hour droplet generator lifetime
  • In burst power of 375 W, in lab
  • Designs now available for 1 kW EUV source based on FEL emission in compact storage ring, and these designs need to be evaluated.
  • Discussions continue for which technology will support 1 kW EUV sources: plasma or free electron laser (FEL)/accelerator based approaches. Work is continuing in Japan on FEL based sources for EUVL.

 

Pellicles

  • Pellicle films produced without defects that print on wafers.
  • Pellicles for NXE:3400B can withstand 140 W. Y-nozzle cooling is expected to extend this to 205 W.

Resist

  • Continued work on fundamentals and evaluating performance of new resists. Metal oxide (MOx) resists provide opportunity to reduce LWR via etch and enable co-integration with newer integration schemes.

 

Mask

  • 100x reduction in overspray reported by Veeco, resulting in reduced mask blank defect density
  • Ion beam target overspray, target nodule formation, and particle entrainment in the ion beam, are potential ultimate limitations to particle reduction in ion beam deposition (IBD).
  • Veeco proposed Biased Target IBD and Target Confined Plasma as alternate deposition technology to IBD in long term.

 

  1. New Additions to existing list of challenges for EUVL (Since 2017 SPIE AL meeting, please see previous blogs (Challenges at various future nodes and Update from 2017 SPIE AL)for a complete listing) and for detailed technical information review Proceedings of 2017 EUVL Workshop or Summary of 2017 EUVL Workshop.

 

7 nm

Nothing new 

5 nm

Need for 350 W pellicles

3 nm

Need for 500 W pellicles

2 nm

1 kW power may be needed. How far can we stretch the LPP technology (laser power, droplet generator, contamination)? What are the challenges for FEL?

What will be the pellicle requirements?

New cap layers for Mask and optics

Understanding EUV Lithography Basics and Status – Key Concepts

By Vivek Bakshi, EUV Litho, Inc.

For a better understanding of EUVL’s status, challenges and opportunities, it is important to study its fundamental components. There are several, with the main ones being source, mask, optics, imaging and resists. They are very different from those in the current 193 nm immersion lithography, and a comprehensive overview of these components is a must. Hence, in the annual EUVL Workshop we dedicate one full day to a study of fundamentals with experts. Here I will tell you briefly about them.

EUVL is basically an optical projection lithography, but with many twists. The main reason for this is the 14x decrease of wavelength to gain on resolution, while previous reductions have been much smaller, like 1.5x. This steep decrease in wavelength requires us to work in a new region of physical properties of materials, in greater depth than we have done before.

The EUV light source is the most complex part of EUVL, and it took the most effort and time to develop. This technical feat is truly doing “rocket science” in the fab. This source was a potential showstopper at one time and now it is the key enabler for EUV for today, and for future extensions. Times have changed! For scanners, we use tin based laser produced plasma sources, but for metrology many other types of EUV sources are used and few others being considered. We will discuss technology, challenges and potential of these sources and their metrology.

Inside the EUVL scanner we use mirrors instead of the lenses used in 193 nm scanners. EUV optics, once considered impossible to manufacture, today is ahead of the curve in needed performance. But there is always more work to be done to get ready for the next nodes. EUV optics and optics chain design in an EUV scanner add unique properties to EUVL patterning. Just like optics, EUV mask is also made of multilayer mirrors with several additional levels of complexity – off-axis illumination and 3-D effects to name two. We are also learning to deal with mask defects, cleaning, defect detection and now pellicles.

Patterning with EUV involves dealing with 3-D effects, flare, new illumination and unique EUV specific optics designs. It now works like a charm, but lots of effort has gone into it to. Today, a lot more work currently is being done to extend patterning to smaller nodes with higher numerical aperture (NA) scanners. EUV resists with more energetic photons have a different chemistry and patterning performance. This is making us look beyond traditional chemically amplified (CAR) resists into new chemistries and do additional fundamental research.

Another important question for many small and large, new and established suppliers for various components for chip-making, especially who arrived late to the game, is where their products, supply chains and competencies fit in the EUVL food chain. Getting to know the fundamentals and overview of EUVL status and challenges will make the picture clearer for all. As all components interact with each other, people working in one area of EUVL with benefit immensely with an overview of other areas as well. We hope that a day of going over the EUVL basics will be very worthwhile for those who climb the hill of Berkeley this year to attend the EUVL Workshop. Additional information about this EUVL short course is available at www.euvlitho.com

Progress in Short and Long Term Focus Areas for EUVL

By Vivek Bakshi, EUV Litho, Inc.

Latest news on EUVL technology status is a topic of much interest to community involved in making high‑end next generation computer chips. Next month, we will have the leading EUVL suppliers, chipmakers and researchers in Berkeley giving us the updates on short- and long-term focus areas for EUVL. I would like to summarize what I expect to be the highlights and their significance for us.

Focus on EUVL is on two fronts. First is progress in the short-term focus area that will decide how quickly, as well as how effectively (throughput and cost of ownership or COO) EUVL is being used in fabs. Topics in this category are source availability (which relates to cost of ownership), pellicles and patterning status.

We will have a manufacturing update from ASML, GlobalFoundries and Intel on these topics in their keynote and invited talks. Gigaphoton (GP), 2nd supplier of EUV sources for scanners, will talk about their new collector design with a longer lifetime (hoping for a better COO). Inpria and JSR will provide updates on the progress of EUV resists. An invited talk from IMEC will give the latest on patterning performance of EUVL from their fabs – where they are working with leading chipmakers and suppliers to prepare EUVL for manufacturing.

The second topic relates to longer term progress, as EUVL is a multi-node patterning technology expected to take us to the end of Moore’s Law. Top topics are higher NA (0.55) EUVL scanner, pathways to increase power closer to 500 W and even higher, actinic patterned mask inspection (APMI) and resist performance (stochastics, LER, micro-bridging, etc.). We will have invited talks from ASML and Zeiss on optics and design of high NA scanners. Both ASML and Gigaphoton will talk about their power scaling plans, together with several papers on EUV source fundamentals needed to ensure scaling.

I am excited about the new free-electron laser (FEL) based technology from Lyncean that they claim can provide standalone 1 kW EUV Source, based on FEL. KEK from Japan is also going to report on the progress on their FEL based EUV source technology. As APMI tools using conventional EUV sources have not been ready, the focus has moved to HHG based EUV sources for enabling mask defect inspection. These tools use alternative imaging and processing techniques, which will be described in several papers. There will be a keynote talk from Prof. Margaret Murnane, whose company has been a leading supplier of HHG sources and now plans for its increasing use in the support of lithography, including mask inspection. Veeco, maker of EUV mask blank deposition tool, used by all mask blank makers, will report on the progress of their technology to further reduce mask blank defects. There also will be several papers on resist fundamentals, which is a key knowledge enabling EUV resist readiness for future nodes.

Like previous years, we expect to hear good discussions and to generate new ideas. We plan to deliver lots of new information in just two days (over 40 papers including a poster session, which is more than many other larger conferences) in a more personal and informal setting. The workshop is from June 12-15, 2017 at CXRO in Berkeley, CA. More information is at www.euvlitho.com.

A final note: I believe that for better understanding of EUVL – status, challenges and opportunities – it is important to study its fundamental components. There are several components (source, mask, optics, imaging and resists) and they are different than current immersion lithography. At least a comprehensive overview of these components is a must. Hence, in the EUVL Workshop we dedicate one full day to study of fundamentals with experts. So please look for my next blog, “Understanding EUVL Basic and Status – Top Key Concepts,” at this site for further details.

Further Thoughts from the 2017 SPIE AL EUV Lithography Conference

By Vivek Bakshi, EUV Litho, Inc.

Stochastics, Lent, Reporting on Conferences, Reality of Things, and a New SEMATECH

In the previous blog, I listed technology status and would now like to discuss a couple of topics in detail. During last year’s SPIE AL conference, the message for EUVL was “Not If, but When.” This year the message was “Not If, but When and How Much Volume.” It was nice to see the technology that I bet on so long ago coming so far and doing so well.

Stochastics and LWR – Why This is not the End of EUVL and Optical Projection Lithography

The stochastics of photons and material were in the focus during the conference. One presenter even called it the cause of the “end of EUV and lithography.” Line width roughness (LWR), or the non-uniform and wiggly shapes of lines that form tiny electrical wires, affects the electrical properties of the circuits that we are working to produce in the end. Although these properties are better for circuits made with EUV compared to multiple patterning, EUV has a serious stochastics challenge as there are 14x fewer photons. I believe that that stochastics will be addressed in some ways and we must remind ourselves that our goal is not “patterns on resists,” which is an intermediate step, but to make “tiny patterns” in the material under the resist. We can beat the apparent limit of physics in how nicely we can transfer the image from mask to resist by finding solutions after the intermediate steps, as I elaborate on below.

First, LWR is not a new story. Back in the nineties, when 193 nm lithography was being developed, I was working in the ATDF fab at SEMATECH developing etch processes. I was told by many that LWR would kill 193 nm litho, as printed lines indeed looked terrible on resist, as well as when those images were transferred to the material below to form lines and contacts. I went to the library (yes, in those days you actually went to the library) trying to figure out the source of this problem, but did not get any clues. In the end by trial and error, I found that a special post-resist patterning etch, initiated before the main etch, could clean up the pattern and drastically reduce LWR. I published a paper on it and did not think much of it at that time. This post-processing of resist patterns, now combined with post-litho rinses, new underlayers, new resist chemistries, litho- dep- etch optimization, flexible pupil illuminations, and innovative mask optical proximity correction (OPC) tricks, are among several knobs available to turn down LWR. Again, remember that resist image is only an intermediate step to what we are trying to do.

At this point, we need to remind ourselves that the Rayleigh criterion of resolution limits how small we can print using a given wavelength. However, we would not be printing what we can today if we had stopped at this resolution criterion. We have been overcoming this limit via OPC and other tricks, and the factor that quantifies our capability to print smaller is called k1. A whole industry emerged around how to take k1 as low as possible. When we approached the diffraction limit of 0.25 for k1 value, it was overcome by multiple patterning and the process continued. Eventually, to continue to print smaller and smaller in the quest toward atomic-level patterning, Litho needs to work together with deposition, etch and metrology. This is already happening, as demonstrated by several papers that showed joint development with etch suppliers.

I propose that the industry develop another factor like k1 (maybe call it s1) to measure how much we can reduce the effect of stochastics, with our goal being low s1 processes.

It is worthwhile to say a few things about Moore’s Law and its projected end by many. I believe that Moore’s Law in its true spirit is not only about physical scaling of the transistors, but also about the scaling of technology to allow ever-increasing information processing. I see transistors as “units of information processing.” We will get to the limits of the current mode of scaling at atomic level patterning with circuit parameters that cannot be gainfully further improved, but that is not an end to scaling of the speed of information processing. In the end, we must switch to different technologies like quantum computing to continue the pace. However, I see no end in the next decade for the current form of scaling. Let us not forget that developing technology for scaling is not cheap, and not without lots of effort.

Lent 

Ash Wednesday usually falls during the SPIE AL conference. Cathedral Basilica of St. Joseph is around the corner from the Fairmont in San Jose, where I usually stay. It has a beautiful interior and is worth a visit. I usually walk the blocks around the church until I get my required steps on Fitbit, and ponder on what I am going to give up this Lent – things that I very much enjoy and have not worked for me. This year, it surprisingly appeared to me that the trade press was also observing Lent and had given up mockery and negative coverage on EUVL, which usually starts on Sunday after Nikon’s Lithovision meeting, even before the start of the actual SPIE AL conference. It was unusually quiet this year on reporting. 

Reporting on Conference News

Toward the end of the week, there were some press reports which contained some inaccuracy. During the conference, one keynote speaker complained to me that he was incorrectly quoted by the media. Another keynote speaker was widely quoted as saying something that was not said in the presentation.

I do not blame the press fully for this, as there is an inherent difficulty in news reporting of technical conferences. Those who are familiar with scriptures know this is a challenge that humanity has faced since ancient times –reporting on complicated things from a distance. The Bhagwat Gita starts with the inquiry of the blind king Dhritrashtra, who asks an expert, Sanjay, to report on what is happening in the far away battlefield (dhramshetra kurushetekimkurvat Sanjaya – in the battlefield at Kurushetra, dear Sanjay, tell me what happened?). It’s interesting to note that Sanjay himself was not at the battle and had to rely on other means to tell the story – such is the case for many of us who are basing their reports on what is being told by someone in the conference. I cannot blame the press too much, having myself missed on a couple of points now and then. 

Reality of things – Lessons from Zen with Relevance to our Industry

As my Zen teacher says, We like the idea of things but not the reality of things. Ordinary coping is an attempt to shape our experience to always match our idea of things. If our experience maps onto our precious idea of things, this is called ‘happiness’ or ‘satisfaction’— getting what we want. This, we are taught, is the purpose of our lives and where we will find real meaning— it is the foundation for enjoying success.” In Zen training we practice turning toward and engaging with the bare reality of things. He further adds, “We are not continually trying to shape ourselves or the world to fit our idea of things. We are meeting things just as they are and yet working with them as skillfully as we can. Zen practice encourages and supports this skillfulness.”

When the industry got to immersion lithography, the biggest challenge was how to get rid of bubbles in the water. We certainly need to do a lot more and solve problems on many technical and infrastructure fronts. EUVL indeed is complicated, as it not only involves a new type of scanner but also changing the infrastructure for mask, resist and modeling. Materials, high temperature plasmas, lasers, contamination, fabrication and metrology— you name it. Moore’s Law did not say that scaling is going to be easy or inexpensive– it just said that it will happen.

I may be the only person in the world who believes that “EUVL IS NOT LATE,” and that “WE HAVE DONE WELL” with EUV technology development. Let us not forget how much time it took us to get immersion fully working, even though we had many fewer problems. The investment now is going to pay off. Chip makers know best, and so have decided on EUVL.

New SEMATECH

One last thing. During the conference I ran into Mark Melliar-Smith, ex-CEO of SEMATECH. it was a nice surprise, as I thought he had retired some time ago. I had just finished putting up an award on my office wall that I got from him many years ago. Seeing him reminded me of good old days of the semiconductor industry, when companies got together to address infrastructure challenges and consider technical challenges where success was not guaranteed. We saved money and tackled big challenges. It had to be done then, and later on we got away from the idea. It may be time to think about a new SEMATECH regarding efforts to extend Moore’s Law. In my previous blog, I listed many things that a New SEMATECH (if we ever have it again) could do, like considering stochastics at the 5 and 7 sigma levels, new resist chemistries, and new types of sources such as those proposed by PSI. We will not get zero defect mask blanks without considering new materials, ultrafine polishing techniques and contamination control options. Chip makers (it is usually Intel which spends more than others) cannot do this alone, and suppliers cannot afford to look at these challenges on their own, either. If we want to pursue new frontiers to continue pushing Moore’s Law forward, we need a new consortium like SEMATECH. I do not mind wishing for things, as that is the first step for things to happen! I leave you with a favorite quite from the Persian poet Hafez:

“I should not make any promises right now,
But I know if you
Pray
Somewhere in this world –
Something good will happen.”
― Hafez

 

2017 SPIE Advanced Lithography – EUVL Conference Update

By Vivek Bakshi, EUV Litho, Inc.

To simplify the vast amount of information from the 2017 SPIE AL EUVL Conference for my blog, I have adopted a new format. It includes a short summary of EUVL Status, a list of notable updates, and additions to the current list of EUVL Challenges (previously published on this site). An additional commentary will follow this blog.

  1. Current EUVL Status 

Source: Current power of 148 W corresponding to 104 wafers per hour (WPH) scanner throughput in-house at ASML. Stable 130 W noted in field. 375 W in lab EUV sources in burst mode at 50 KHz. 200 W of stable power is possible in field in 2017. Source power now meeting requirements for introduction of NXE3400. Current source availability at 75%, needed at >90%. Droplet generators and collector lifetime improving but need further improvement.

Scanners: Fourteen EUVL scanners in field. Four shipped in 2016. 0.3 nm critical dimension uniformity (CDU) and 1.8 nm overlay. 148 W and 104 WPH with increase of 8 wafers per hour (WPH) achieved via increase of stage speed at the same source power.

Masks: Mask blank defects acceptable for now via defect avoidance and repair.

Mask Pellicles: Mask defect addition during manufacturing is still a concern for chip makers. Pellicles are at 125 W and need to be ready for 250 W by 2H 2017. 

Mask Defect Inspection: Samsung has made its own AIMS tool and plans to use it for high volume manufacturing (HVM). Tool is using HHG based EUV source and a scanning zone plate. Zeiss is now shipping its first AIMS tool. Actinic Patterned Mask Inspection (APMI) tool still missing. Mask defect inspection via wafer inspection for now, at a cost and with lower yield. APMI is only red flag item for 7 nm insertion of EUVL. 

Resist: Lots of talk about stochastics, but I believe it will be addressed and it is not a showstopper. Important to note that resist image is only an intermediate step and there are still several knobs available to improve the performance of the final circuit – which is what matters.

  1. Notable Updates 

Scanner and imaging

  • Increase of throughput by 8 WPH via greater stage speeds is first such increase, with more to come. Now expect source power of 210 W to give 125 WPH instead of 250 W (increase in throughput via stage speed improvement)
  • Extension of EUVL to low k1 may be more difficult than for 193i. Discussion of various factors and how to address them has started.
  • More enthusiasm for high NA scanner, as it can help with line width roughness (LWR) and extension to lower k1. Detailed checklist of High NA challenges from Samsung.
  • Data showing that around 5 sigma errors deviate from standard distribution. We do not understand error distribution behavior at 5 to 7 sigma (it is no longer a normal distribution). We now need to print one trillion vias in one exposure with no open! 3 sigma is no longer enough.
  • Closer cooperation among litho, etch and deposition is the way to reduce EPE and address stochastics. Work has already started.
  • Scanner to scanner variation higher for EUVL than for 193i. How to address this in optical proximity correction (OPC)? Will this lead to scanner specific EUV masks?

Source

  • Need to better understand source power requirements for 3 nm and beyond. How much additional help we will get from scanner for increasing throughput? Is 500 W enough? Will we need additional power?
  • Power scaling to 500 W is still lots of work and not a done deal as conversion efficiency decreases at higher pulse energy (favored method for power scaling). 

Resist

  • Introduction at 7 nm planned at 20 mJ dose
  • Micro bridging (aka nano bridging) of resist is a new challenge reported by several people. Its relationship to dose, type of resist and LWR is not clear. Some said that this may become bigger than LWR issue. Papers showing OPC and Litho- etch optimization can help reduce this effect.
  • Continued work on chemically amplified resists (CAR), metal based inorganic resists and molecular resists to support 7 nm and beyond.
  • Out of Band (OOB) filter in now in scanner that also acts to keep resist outgassing products out.
  • Sigma alone may be insufficient to characterize LWR. New additional variables needed? 

Mask

  • Replacement of current mask absorbers by Ni to improve imaging. Continued review of new mask structures with improved imaging potential, but patterning challenges exist for these new stacks.
  • Need source mask optimization to address 3D mask effects.
  • High sensitivity to Pellicles defects for small pupil fills imaging
  • Need for further analysis and reduction of defects in the scanner, that end up on masks, generated during manufacturing.
  • Current fixed pellicle design needs to evolve to provide future solutions.
  • New carbon nanotube based pellicles from IMEC
  • New APMI design from PSI/ETH, supported by small synchrotron based EUV source.

New terms heard at SPIE AL

  • Etch Color, CD healing, Black Swans (at seven sigma), Vote-taking Lithography (resurrection of a 1986 idea to move away from 100% defect free mask requirements), nano bridging and micro bridging of resists, and Tone inversion.

Most Interesting Papers

  • Couple of papers on stochastics – Line edge roughness (LER) performance targets for EUVL (10143-10) by Tim Brunner of GlobalFoundries and Lithographic Stochastics – extrapolating to 7 sigma (10143-31) by Robert Bristol of Intel.
  1. Additions to existing list of challenges for EUVL

7 nm

Nothing new

5 nm

Micro bridging of resists

Error distribution at 5-7 sigma 

3 nm

Power scaling to 500 W and beyond

Micro bridging of resists

Error distribution at 5-7 sigma

Areas of Focus and List of Challenges for EUV Lithography at 7nm, 5nm and 3nm Nodes

By Vivek Bakshi, EUV Litho, Inc.

As we look forward to 2017 SPIE Advanced Lithography Conference in San Jose next week, the focus once again will be on EUV Lithography, its readiness for manufacturing and plans of chip makers for starting to use EUVL in their fabs.

Insertion is planned from 7 to 5nm nodes by chip makers in coming years. The areas of focus at 7nm are mostly related to productivity and uptime goals of sources in addition to pellicle. The 5nm insertion has few other areas come into focus where more work is needed like actinic inspection, resist readiness and mask blank defectivity – although none of them is a showstopper.

List of challenges pick up lot more at 3nm node, as we consider high NA scanner, corresponding newer design for EUV masks and need to for upto 500 W of source power. A detailed list of these challenges is worth a review and is now published at the website www.euvlitho.com as topics for 2017 EUVL Workshop in June 2017. I will be updating this list after as well as sharing my opinion on the latest with EUVL in coming weeks after this year’s SPIE AL meeting.

Bringing you Holiday Cheers – Courtesy of Moore’s Law

Vivek Bakshi, EUV Litho, Inc.

Author’s preface: This article is a departure from my usual high-tech language, because I think our industry needs to do more to educate non-technical readers about how their treasured electronic devices got to be so cheap and powerful. Our success in realizing Moore’s Law has been one of the greatest achievements in modern science, and we must continue doing all we can to continue that progress. Please feel free to share this essay as a holiday gift to anyone in your life who benefits from the achievements of lithography.

For many, our Christmas holiday cheer is wrapped around getting the latest gadget that brings us more power to do things than we had the year before ‒ be it a new iPhone, iPad, laptop or some other high-tech gizmo. Added to this annual ritual, which we now intuitively expect but do not quite notice, is that we pay less or the same for these gadgets than we did in previous years – even though they may run twice as fast and store three times as many photos and videos. At the heart of this happy surge are the computer chips that grow more powerful every year without increasing their price. I would like to tell you how we in the computer chip industry do this, and what it will take to continue this trend in the coming decades.

Technology was not always like this. Growing up in the early 80s in India, where my dad worked for the telephone company, I remember that when we got a new phone it was the same rotary dial model with just a new exterior body, and maybe a new color. If today’s technology were moving at the same speed as then, we would only be getting a new cover for our iPhone or a new computer mouse for Christmas, and not more powerful gadgets.

To understand this phenomenon, we need to look at the leading-edge computer chips that are the heart of all these tools, made by leading chipmakers like Intel, Samsung and others. Inside these microchips are tiny transistors and other circuit elements that do the work. The reason these devices can deliver more power every year at lower cost is because the advancement of computer technology is guided by Moore’s Law, named after Gordon Moore, co-founder of Intel Corporation. Moore proposed this law in 1965, saying that number of transistors per square inch would double every two years or so.

We have been able to follow Moore’s Law so far by making transistors and other circuit elements smaller every year. Making computer chips takes many steps, the most critical of which are embodied in a process called Lithography, which involves printing the images of circuits. To print smaller and smaller transistors, we need to be able to resolve the printed images. British physicist Lord Rayleigh (1842-1919) pointed us to “knobs” that we can turn to resolve ever-smaller images. Prominent knobs are color of the light for printing (wavelength), design of optics (numerical aperture) and printing under something more dense, like water. We also have also learned lots of tricks (called optical proximity corrections and multiple patterning) that let us keep on printing smaller and smaller features.

The current technology of choice for advanced printing of computer chips is called 193 nm optical projection lithography, which involves a zillion optical tricks and repeats the printing process three or four times to make one image. However, 193 nm has been running out of steam for some time. This means that either we cannot make computer chips more powerful by just shrinking the size of features, or the cost of doing so will be a lot more. Neither of these are acceptable solutions, and that is where Extreme Ultraviolet Lithography (EUVL) comes into play.

EUVL promises to extend Moore’s Law by changing the color of light used for printing – from current 193 nm light from excimer lasers to 13.5 nm light from plasma sources. Alas, we cannot see either wavelength with our unaided eyes. This switch of color came with big physics challenges as EUV Light, with its photons of 14x energy, interacts with matter very differently than photons from excimer light. This change has resulted in a massive amount of work over many decades on light sources, optics and photo-sensitive chemicals for developing images. For these reasons, EUVL has taken many decades of worldwide effort and investment and is now expected to be used by leading chipmakers by 2018- 2020 time frame.

We would certainly be lost without the ever-more powerful computer chips that we are now used to having at our disposal every year. So now you know whom to thank for your new holiday gadgets, and you can rest assured that they will keep on working to ensure the benefits of Moore’s Law will continue for years to come.

Highlights from 2016 EUV Source Workshop – Work on Conversion Efficiency of EUV Sources and Continued Progress in Source Technology

By Vivek Bakshi, EUV Litho, Inc.

The 2016 Source Workshop was held Nov 7-9, 2016 at ARCNL, Amsterdam, The Netherlands. During the workshop we received new information about EUV source power, updating what we learned at the EUVL Workshop in June. ASML now has 125 W sources in field with their uptime improving, and 210 W dose controlled sources in lab, with 5.5 % conversion efficiency (CE). This leads me to predict that we will be able to have 250 W in field by 2018, which will be needed to support manufacturing at 125 wafers per hour. Another piece of good news on the high power source front is the continued solid progress by the second-largest supplier of HVM EUV sources, Gigaphoton. They now have 100 W @ 5% CE, with 95% duty cycle for 5 hours of continuous operation.

There were reports of continued progress on EUV metrology sources, but they are still years away from being integrated into the next generation of mask defect inspection tools. In the workshop, I heard that Zeiss is now working closely with suppliers to evaluate their EUV metrology sources for their next generation AIMS tool. We also need patterned mask inspection (PMI) tools to be ready sooner than later, and I was happy to see a presentation by KT on the status of the source for their PMI tool. However, when and if this tool will become reality is still unknown, while these tools will be needed at 5 nm application of EUVL in fabs.

This year there were several papers (experimental and theoretical) on how to increase CE of sources by looking deeper into the working of EUV sources. In EUV sources, the laser energy (which is at 10 micron wavelength) is converted into 13.5 nm photon. Current reported CE is 5.5 to 6%. Can we can get more efficient?

We learned, via plasma measurements, how we can better tweak the delay and shape of laser pre-pulses (Kyushu University papers) and were told about development of pre-pulse lasers to enable the delivery of those optimum pulses (work from HiLase).

I found interesting the work of Hanneke Gelderblom, Univ. of Twente and Dmitry Kurilovich, ARCNL. They are using “water drops as scale model for tin” to understand the scalability of hydrodynamic stability of droplets interacting with lasers. They found that they can adjust parameters to work in regions to avoid drop breakups during interaction of laser with droplets, while looking for greater laser absorption to increase CE. It was a good example of how we can use learnings from other disciplines to improve the functionality of EUV sources.

Gerry O’Sullivan of UCD pointed to the need for maximizing the line emission by reducing opacity and reducing recombination. He noted that plasma density has a “sweet spot” for a maximum CE and optimized CE. He also described his wedged target colliding plasma that can be better matched to CO2 for increasing CE.

A most interesting CE paper to me was one by Mikhail Basko. He pointed out that in principal, 20% CE is possible (based on 40% spectral efficiency calculations) but in reality only 9% CE can be achieved. He pointed that 2.5% of CE is lost as the kinetic energy of plasma flow, while rest of CE is dissipated due to non-uniformity of temperature across the “working” zone and in-band reabsorption. We need to find ways to achieve this optimum density profile in our tin targets to get to 9%.

There were several interesting papers on modeling efforts to improve CE (LLNL, ISAN, Cymer) and generation of fundamental data to improve modeling. Such efforts are going to be important as we run out of knobs readily available to us today to improve CE, and we must look deeper into the working of plasma sources to squeeze those additional EUV photons out of plasma and search for stable operational modes for sources that can be sustained in factories around the clock.

We had many excellent papers on XUV sources and their applications to support manufacturing in the semiconductor industry and beyond. Hans Hertz in his keynote speech described his water window microscope, which with a 200 W laser of 600 picosecond pulse operating at 2 kHz gives an early synchrotron level of brightness. It can now do 3D tomography with a 10s exposure. These developments were possible due to a new multilayer mirror with >4% reflectivity (optiXfab) at water window wavelengths. He had reported the development of these new multilayer mirrors in last year’s source workshop, and decided to incorporate them in his tool to achieve this progress.

This year’s workshop had the highest attendance ever. I was happy to see continued work by the research community and suppliers to better understand the working of EUV sources, so that we can achieve those 500+ W sources that can operate 24/7 in fabs with 80-90% uptime.

Pushing Frontiers of EUV Source Technology – 2016 Source Workshop (November 7-9, 2016)

By Vivek Bakshi, EUV Litho, Inc.

EUV Sources remain the key component for ensuring EUV Lithography’s entry into fabs for high-volume manufacturing. Two big factors that have enabled dramatic progress in source readiness are related to improvements in source power and source lifetime. Now the question is how far we can push source power and lifetime, and what is needed to enable continued progress.

For answers, we need to look into the fundamentals of plasma based EUV sources, as well new engineering designs. The present conversion efficiency (CE) of sources is a couple of percent, while the theoretical maximum approaches 8%. If we are at 2.5% CE today, it means we can get ~ 3 times more EUV photons from the same level of energy input, if sources could be operated closer to 8% CE. The lifetime (optics and fuel delivery system) also needs to be such that 90% uptime goals of tools can be met.

During the upcoming 2016 Source Workshop, we will have papers taking a closer look at these topics. There are several papers on how to increase the CE of sources to allow us to get more source power. There will be another session on plasma dynamics of EUV source to further our understanding and enable newer designs of sources that will help bring about better CE and longer source lifetimes.

Another important topic is EUV sources for metrology. Low power but brighter EUV sources than those available today are needed for actinic inspection of masks. We will have new potential designs from five suppliers for actinic EUV sources, as well as papers on high harmonic generation (HHG) and free electron laser (FEL) based sources for EUVL. In addition, we will have sessions on XUV sources and their application in patterning and other industrial application like water window microscopy.

I look forward to these new ideas and updates in the EUV and XUV source technology area. The Source Workshop this year is in Amsterdam, The Netherlands, held in conjunction with ARCNL. Dates are November 7-9, 2016 and additional information is available at www.euvlitho.com.