Insights From Leading Edge


IFTLE 363 IMAPS 2017 Part 4: DARPA SHIELD; Shinko embedded die for PoP; Rf Interposers

By Dr. Phil Garrou, Contributing Editor

Hope all my readers in the USA had a great Thanksgiving. For those of you around the world, this holiday occurs in late November in the US when families get together for a 4-day weekend. I was with my two sons and my granddaughters Hannah and Madeline (who you have watched growing up ) in Houston and it was great to spend some time together. Younger son Christopher, who is a Chef in Maine, joined us and helped with the cooking activities.

Thanksgiving

 

Now let’s finish our look at the 2017 IMAPS Conference.

Northrup Grumman

Under the DARPA/MTO SHIELD program Northrup Grumman led a team of GaTech, Sandia, Kilopass and RFID Global solutions have developed a supply chain traceability and authentication method to protect against counterfeit electronic parts. The solution consists of the incorporation of a 100 x 100 x 20um “chiplet” (they call dielet) fabricated in 14nm CMOS. Authenticity is verified using an Rf probe to energize and communicate with the chiplet. Putting the size of the chiplet into perspective, the pic below shows the chiplet on the head of Lincoln on the back of a penny.

NG 1

The chiplets are manufactured using GlobalFoundries 14nm FinFet technology. The 300mm wafers are thinned and the 20um dicing streets result in ~ 4MM chiplets per wafer. Pick and place of these tiny chiplets is “challenging” but they have developed a technique to insert them into the host packages. Process flow is shown below:

NG 2

Shinko

Kyozuka of Shinko discussed the “Development of Thinner PoP Base Packages by Die Embedded and RDL Structure.”

PoP structures can achieve thinness by embedding a die (or dies) into a package thus achieing height reduction for devices like APS (application processors). Their “die embedded with RDL” structures are shown in the fig below with design specs.

shinko 1

The process flow is shown in the fig below.

shinko 2

The FC process is done by TCB (thermos-compression bonding) followed by capillary underfill . After die mounting the cover layer of laminate is vacuum laminated and vias are laser drilled to make connection between the substrate and the top RDL. Expected issues with warpage were controlled by controlling layer thicknesses and copper density on the layers.

Via formation included laser drilling, desmear, electroless and electrolytic copper plating. Vias were tested under condition B (-55 to 125◦C) with 75 and 100um visa passed such testing.

IMEC

Bart Vereecke of IMEC discussed “Investigation of wafer level packaging schemes for 3D Rf interposer multi-chip module”. The fig below schematically shows the structure with a GaAs MMIC mounted on the silicon interposer. The interposer consists of two metal levels sandwiched around a MIM cap layer. A Cu/Ni/Sn seal ring is designed in for bonding Si cap layer. The interposer is made of high resistivity Si to minimize Rf losses.

IMEC 1

They examined different wafer level packaging approaches for fabricating the interposer and populating them using either D2D or D2W bonding of the MMIC components followed by wafer level encapsulation. These are compared in the table below. All of the process flows appear to have issues.

imec 2

Axus Technology

Bob Roberts of Axus presentation “Technology transfer for MEMS and Adv Packaging” was a nicely written review of the use of CMP and the thinning of silicon wafers which I can recommend to those wanting a refresher on the technology.

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 362 Broadcom Continues Consolidation; IMAPS 2017 Part 3

By Dr. Phil Garrou, Contributing Editor

Before we get back to the IMAPS 2017 conference, a few important items:

Consolidation – and the beat goes on

We have talked a lot about consolidation and why it is happening. [see IFTLE 255 “Consolidation continues …” and IFTLE 241 “Simply Obeying the Laws of Economics” ]

On November 6th Broadcom announced its intention to buy its rival, Qualcomm, for ~ $130B, including debt. If successful, it would be the largest deal in the history of the technology acquisitions. Following the consolidation trail, NXP acquired Freescale and Qualcomm is trying to acquire NXP and Broadcom is trying to acquire Qualcomm. Certainly a sequence that no one could have predicted a few years ago. If Broadcom successfully acquires Qualcomm, the combined group would become the world’s third-largest chipmaker, behind Intel and Samsung. If they combine, with no divestments, Qualcomm and Broadcom would control between 50%-60% of the market for Wi-Fi chips and 27% of radio-frequency chips for mobile devices.

The Economist offered the following table listing mega mergers (consummated and in process) [link]

economist 1

The Economist also offers the comment that “with Qualcomm’s pending purchase of NXP and Broadcom’s of Brocade, what looks at first glance like a merger between two giants is actually a four-sided deal. It would be difficult to unite so many different divisions and business units all at once” It certainly will be interesting to see what happens here!

Continuing our look at IMAPS 2017

InFO like FOWLP from ASM Pacific & partners

John Lau representing ASM coauthored the presentation “Fan out Wafer Level Packaging of Large Chips with Multiple Redistribution Layers” with a long list of co-workers. The design is a chips first face up process looking a lot like the TSMC InFO. The detailed descriptions of the processing are much appreciated. The overall process flow is shown below.

asm 1

 

As is the case for InFO the key processing sequence is plating up the contact pads on the wafer (30um), molding the wafer and hen grinding back the mold cmpd to expose the copper pads much like you would a TSV. Their mold compound is Nagase R4507 a liquid EMC with 85% filler content and an average filler particle size of 8um.

Subsequent processing of the RDL layers is shown below. The smallest L/S features on the bottom RDL layer is 5/5.

ASM 2

 

From this groups 2nd paper “Characterization of fan-out WLP” we learn that

– die attach accuracy and pitch compensation are the key issues that need to be controlled for accuracy in the RDL process

– die tilt is an important factor that affects the contact pad reveal so the die bonder should be optimized to control leveling

– molding concerns include die shift, warpage and voids. Mold cmpd choice will affect warpage results.

Namics & Hitachi Chemical

The presentation “Development of Liquid Compression Molding (LCM) Materials for Low Warpage” by Namics and Hitachi Chemical detailed the properties required for a low warpage LCM. They were able to substantially reduce LCM warpage by using aliphatic, flexible epoxy resins with low modulus and low cross link density.

Hitachi Chemical

Hitachi Chemical also detailed their studies on “Highly Reliable Cu Wiring Layer for 1/1um L/S using newly Designed Insulation Barrier Film.”

It is generally agreed upon that organic substrates fabricated by the semi additive plating process is limited to 8um L/S . To achieve finer interconnect pitch required by future FOWLP Hitachi Chem has studied trench wiring to create such high density structures. This sequence is typically laser ablation of the trenches in the dielectric, copper plating and subsequent planarization by CMP. Barrier metal is required to minimize copper migration so the seed layer for plating is generally 50nm of Ti followed by 100nm of sputtered Cu. The processes are compared below. For reliable HAST testing of 2/2 L/S they have found that covering exposed Cu with a Ni barrier layer is required.

Hitachi chem 1

They have also examined chemically amplified, negative tone, photosensitive dielectrics to achieve below 2/2 L/S. This processing includes the use of an insulation barrier film which shows low moisture absorption, low anionic impurities and high hydrolysis resistance. Using this combination they were able to achieve 1/1 L/S.

hitachi chem 2

For all the latest in advanced packaging, stay linked to IFTLE…

ITLE 361 2017 IMAPS Part 1: Xilinx HMB Integration Challenges and More

By Dr. Phil Garrou, Contributing Editor

Let’s start looking at some of the key presentations at IMAPS 2017.

Xilinx

Gandhi of Xilinx gave an interesting presentation on “2.5D FPGA-HBM Integration Challenges.”

Heterogeneous integration of HBM (high bandwith memory stacks) with ASIC, GPU, CPU and FPGA is real and progressing quickly. Xilinx is the frst company to attempt HM integration with partitioned FPGAs in a 2.5D format.

Xilinx 1Xilinx recently announced HBM enabled 16nm Ultrascale FPGAs which are shown below. They are built using 3rd gen CoWoS technology jointly developed by Xilinx and TSMC. The claim is that these heterogeneously integrated packages are delivering 10X the bandwidth per HBM stack and 4X lower power than DDR-4 . These packages are 55 x 55mm2.

 

Interposer Design – µbump pitch on the memory stacks are set by JEDEC standards. There is no std for µbump pitch on FPGAs. For ease of interposer routing, pitches across the two die need to match so that an integer number of inter die signal lines can be routed in a uniform fashion between a pair of micro bumps. This is also required from a signal timing point of view.

Package Design and Process –

xilinx 2HBM-FPGA integration for the current 16nm product required changes to bump structure and lid type. The packages moved from eutectic solder bumps to copper pillar bumps with lead free solder and a change from a copper lid to a stainless steel stiffener ring was also required. This is shown in fig below. Precise control of bare die parallelism and flatness is required to enable heat sink attachment. In the shown figure, modeling shows that co-planarity is reduced by wider ring width and/or thicker stiffener ring. They were also required to change the BGA substrate to a lower CTE core to lower the co-planarity.

Challenges in bump assembly

Addition of the HBM stacks results in open area around the HBM stacks in the layout as seen in the above pic. This results in higher warpage. Bump size and underfill type must be optimized.

ETRI (Electronics and Telecom Research Institute) Korea

ETRI has examined the “Development and Stacking Process for 3D TSV Structures using Laser.”

As part of their 3D studies they have compared bonding results between using TC (thermocompression) and laser. The bonding procedure is shown below.

ETRI 1

The max temp of the compression bonding was 240 °C for 200 sec at a force of 1 Newton. At a laser power of 200W the max temp reached was 260 °C at a process time of 10 sec.

They concluded that there was no difference in the solder joint morphology and the electrical resistances of bonded daisy chains for both assembly technologies was the same.

KOBUS

Kobus presented a “Alternative Deposition Solution for Cost Reduction of TSV Integration.” Use of TSV requires isolation, barrier and copper seed deposition into the etched vias. For low AR TSV one uses PECVD and PVD techniques for the depositions. For high AR vias ALD is sometimes required. PECVD offers the highest dep rate but poor conformality. ALD results in near 100% conformality irregardless of AR, but the thickness is limited and he dep time is very slow.

FAST (Fast Atomic Sequential Technology) combines CVD and ALD to reportedly rapidly give thick, conformal depositions.

Oxide liner dep from TEOS is compared below.

Kobus 1

Electrical properties of the deposition are reportedly enhanced with 150 °C deposition resulting in BV or 9MV/cm.

TiN barrier layer is from TDEAT (tetrakisdiethylamidotitanium) and copper seed from Cupraselect™. Copper seed dep comparing FAST with PVD are shown below. They report that the field thickness (on top), resulting from copper deposition to get 200nm of copper at the bottom of a 10:1 AR via, is reduced by 2X which effects the subsequent CMP time to remove it.

kobus 2

Claims of a 24% reduction on TSV processing cost are claimed.

For all the latest on Advanced Packaging, stay linked to IFTLE…

 

IFTLE 360 IMAPS 2017 – 50 Years and Counting

By Dr. Phil Garrou, Contributing Editor

IMAPS 50th

IMAPS (the Int Microelectronics Assembly and Packaging Society) 2017 was held this year near their Research Triangle Park headquarters, in Raleigh, NC, certainly a convenient location for IFTLE. Having started operations in 1967 as ISHM (Int Society for Hybrid Microelectronics), they changed their name and focus during my Presidential year of 1998 to IMAPS. This is the 50th year of existence for this nonprofit society. I emphasize the term nonprofit intentionally. This is important to me since the conferences we all attend request we give our free time to serve as presenters or session chairs or organizers and I want to be sure that the profits from such enterprises are going to a nonprofit and not into someone’s personal bank account, as is the case for so many of these conferences you and I attend. Basically, I don’t work for free unless it is a non profit, only seems right to me, so conferences that I give my limited time to, tend to be organized by IEEE and IMAPS.

My first IMAPS conference was in 1985 as my professional focus in Dow Chemical shifted from R&D on organometallic catalysts to the electronics industry. I was 35 but only a rookie in the electronics industry with lots to learn. This was the first electronics conference of my career (which I then followed up with the ECTC conference in the spring of 1986) and as importantly, it introduced me to many of the contacts and long term friends that I was able to develop in this industry through the years.

Fig 1

I recently took a look at the Proceedings (which I still have in my professional library) and during this trip down memory lane thought you might be interested in what was considered groundbreaking 32 years ago.

In the mid 1980s the industry was just getting comfortable with surface mount components and Harry Charles of Johns Hopkins was talking about “Design Optimization and Reliability Testing of Surface Mount Solder Joints”.

In the computer aided design session authors from Tektronix were sharing their thoughts on “Just-in-time Manufacturing – An essential technique for Process Control”.

In the Polymer Applications session, Englehard (that’s right Englehard the precious metals company) was showing us how to spin coat polyimide in their paper “Multi-layering with PI dielectric and metallo-organic conductors.” This paper had a significant influence on my personal career since, working for Dow Chemical at the time, I went back home wondering whether I could find a Dow polymer material that could be used for similar thin film polymer IC applications. This eventually led me to the discovery (it existed in the bowels of Dow R&D without a clear application need) and commercialization of BCB dielectric which by the mid 190s led to the commercialization of low cost bumping and WLP at FCT and Unitive and subsequently all the key bumping houses in Taiwan as they licensed the technology. By the early 2000s, BCB was being used in components put into nearly every cell phone being manufactured in the world!

The interconnect technologies session contained the paper “Recent advances in Die Attach Adhesives for Microelectronics” given by epoxy legend Dick Estes from Epoxy Tech. At the time polymeric die attach were not allowed in high rel military applications. He described the issues of thermal stability, outgassing and most importantly halide contamination of devices.

Kohji Nihei of Oki , later to become infamous as the photographer of the generation that proceeded me, gave the first paper I had ever seen describing the use of “LEDs for the electrographic, non impact printing of text and images” entitled “Development of High Quality LED Print Head” (shown below) Think that’s a technology with a commercial future?

Fig 2

For those of you that don’t remember Kohji, you should, both as a wonderful person and a technologist. Below he is shown a few years later in Japan with the American contingent at an IEEE VLSI workshop.

(l-r) Kohji Nihei (Oki), Len Schaper (AT&T, Alcoa, U. Arkansas), Garrou, Jan Vardaman (TechSearch), George Harman (NIST “Mr. Wirebonding”)

(l-r) Kohji Nihei (Oki), Len Schaper (AT&T, Alcoa, U. Arkansas), Garrou, Jan Vardaman (TechSearch), George Harman (NIST “Mr. Wirebonding”)

That’s enough of the past. Next week, we will begin our look at the 2017 IMAPS Conference content, I promise.

For all the latest on advanced packaging and nostalgia, stay linked to IFTLE…

IFTLE 359 ARM on IoT; SEMICON Taiwan Part 4

By Dr. Phil Garrou, Contributing Editor

Will IoT require “dirt cheap” packaging?

Those of you following IFTLE’s position on IoT know that while I certainly see a future where the wireless collection of data proliferates, I see this, in general, for extreme low cost packaging solutions, certainly not, as some have said in the past, an IoT using 2.5/3D solutions.

In seeming agreement with that conclusion, Rick Merritt of EE Times describing the recent ARMTechCon reports that the panel discussion on “Breakthrough Technologies enabling the future of IoT” concluded that the future of IOT could depend on a chip that sells for less than 50 cents, that SoCs will need new kinds of memories, connectivity and sensors to scale to dimensions the IoT will demand, and that the path to get there is still unclear. [link]

He reports that SRAM and flash memories, Bluetooth interfaces and sensors consume too much power to serve volume IoT nodes in 2027 where ideally, ARM reports, an end node SoC would consume just 10 microwatts/MHz and send and transmit data on a radio drawing only 1 or 2 mW. In terms of transmission, radios need to ultimately scale to power levels of a tenth the power of today’s Bluetooth Low Energy which perhaps will require a new radio maybe on new frequency bands which might take a 10-year effort to execute. Sensors will also need to explore new materials and design techniques to lower power, shrink size and add features. Sensors will need heterogeneous integration packaging technologies to integrate them into modules. “ … so the package becomes the sensor with silicon inside it”. Bottom line seems to be, as we have stated before, that the packaging solutions for IoT will have to be “dirt cheap”

SEMICON Taiwan continued…

Brewer Science

In his presentation on “New Materials for Fan-out WLP,” Tony Flaim of Brewer proposed an interesting new fan out concept where cavities are laser drilled into a laminated sheet, chips are inserted face up into the cavities and thin film RDL is created over the chips as shown below.

Brewer 1

 

SavanSys

IFTLE is not a big fan of making technology decisions based on cost modeling. My past experience has shown that he cost models that I have used are generally very accurate when all the inputs are well known and not very accurate when the inputs are being “guestimated”. Having said that, I do like the slide presented by Chet Palesko of SavanSys Solutions on the general comparison of embedded die vs FOWLP vs TSV solutions shown below…

Savansys 1

ITRI

ITRI always gives us a nice update on activities in Taiwan. Below we see that Taiwan foundry services currently account for 70% of the world wide market and the Taiwanese IC packaging and test services account for 55% of the world wide SATS market.

ITRI 1

Global Foundries

Dave McCann of GF showed a nice process flow for their 2.5D production where the interposer fab, logic fab, memory fab and OSATS must work together to deliver the finished product.

iftle

Next week, we will begin our look at IMAPS 2017. For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 358 SEMICON Taiwan Part 3: ASE & Powertech Fan Out Options

By Dr. Phil Garrou, Contributing Editor

Continuing our look at 2017 SEMICON Taiwan.

ASE

John Hunt of ASE discussed his thoughts on “Fan Out Packaging – Simple to Complex”.

An interesting slide was his chronology of wafer Level (WL) packaging sine the adoption of bumping and RDL (the advent of Taiwan licensing the FCT technologies).

ASE 1-2

Hunt divides fan out (FO) categories into low density and high density options:

  • Low Density fan out

– Less than 500-600 I/O

– L/S > 8µm

  • High Density fan out

– Greater than 500-600 I/O

– L/S < 8µm

Early applications for low density FO include baseband and Rf transceivers. New opportunities include:

ASE 2

Early high density fan out opportunities include PoP and SiP

New Opportunities include:

– APU + memory

– GPU + memory

– Network applications

– SiP/Modules

Note the GPU and Network apps begin to intrude into the space carved out by Silicon 2.5D. Such a product is described below:

ASE 3

Hunt showed the following ASE fan out package platform:

ASE 4

Powertech

David Fang, CTO of Powertech discussed PTI panel level processing developments.

– Packaging for more than Moore modules is usually larger than 10x10mm and thus panel level processing provides 3-5X the efficiency of wafer level even at 300mm.

– They have found that the initial investment per module is 30-40% higher for panel level fan out modules than for fan in WLP.

Continuing challenges for panel processing include:

– No worldwide standards

– Tool and accessory readiness

– Process difficulties, i.e. panel warpage, chip shift, fine line patterning

An interesting slide details their thoughts on panel equipment selection based on technology from the Wafer, LCD and PWB industries.

powertech 1

Powertech fan out solutions are shown below.

powertech 2

For all the latest on Advanced packaging, stay linked to IFTLE…

IFTLE 357 SEMICON Taiwan Part 2: Laser Processing

By Dr. Phil Garrou, Contributing Editor

Continuing our look at SEMICON Taiwan 2017, we’ll look at some of the papers dealing with laser processing for advanced packaging.

Suss

Habib Hichri examined the reliability of ultra fine line redistribution. Redistribution, developed in the 1990s to facilitate bumping or chips designed for peripheral interconnect, is now indispensable for WLCSP, fan out WLP and Embedded IC packaging.

The claim he best process is a dual damascene process flow creating the trenches and vias by laser ablation as shown below.

Suss 1

 

  • Excimer laser ablation patterning does not require photosensitive materials

–allowing wider choice of dielectric materials

  • Ablation patterning is performed after cure
  • Significant reduction in lithography-related steps

–No photoresist application, develop or strip required

ASE

YE Yeh of ASE described their “Laser Technologies In Advanced Packaging and SiP Process” They offered the following use of lasers for their advanced packaging technologies.

ASE 1

Trumpf Lasers GmbH

Michael Lang of Trumpf Lasers discussed Laser application development for advanced packaging.

Ultra short pulse lasers enable extremely precise, cold ablation of different materials as shown below in the comparison of ns and ps lasers. Typical materials used in Advanced Packaging can be machined without heat-affected zone.

trumpf 1

 

Orbotech

Nimrod Bar-Yaakov of Orbotech discussed laser via formation for Advanced Packaging.

They offered the following as key advantages of laser drilling for Advanced Packaging applications:

  • Cost and process reduction: Direct material ablation saves photo-litho processes
  • “Digital Patterning”: adjusts the drilling pattern according to the actual location of the die
  • Same tool and process suites various substrate compositions
  • Laser processing tools are panel format ready

They offered the following process flow for PoP laser ablation of TMV:

Orbotech 1

Pattern-based registration

  • Die placement and process variation can cause misalignment between fiducials and pattern
  • Using actual pads pattern as registration targets can overcome this issue

orbotech 2

They offered further visual evidence that thermal effects are reduced by using short pulsed lasers.

orbotech 3

For all the latest in advanced packaging, stay linked to IFTLE…

ITLE 356 SEMI Taiwan Part 1: Fan-out Packaging Players, Applications and Market Growth

By Dr. Phil Garrou, Contributing Editor

SEMICON Taiwan

Although threatened by Typhoon Talim, SEMICON Taiwan went forward Sept 13-15 in Taipei. Over the next few weeks IFTLE will be covering Interesting advanced packaging disclosures and topics with relevance to advanced packaging. Our thanks to Semi’s Debra Geiger, Jamie Liao and Grace Wang for linking IFTLE to the relevant materials.

CP Hung of ASE chaired the SiP forum “3D IC, 3D interconnection for AI & High-End Computing” and Albert Lan of Applied Materials chaired the forum “Innovative “Embedded Substrate” and “Fan-Out” Technology to Enable 3D-SiP Devices.”

albert Lan

Albert Lan – Applied Materials

CP Hung - ASE

CP Hung – ASE

Let’s first take a look at the embedded and fan-out forum

TechSearch

Jan Vardaman presented the following list of Fan-out WLP suppliers

TechSearch 1

TechSearch lists the following as why Apple chose this TSMC packaging format for their A10 processor

  • Improved electrical and thermal performance of InFO vs. FC-­‐CSP

– InFO PoP Power Noise Reduction and Signal Integrity Improvement

  • Thinner than flip chip package (no substrate)

– InFO-­‐PoP is 20% thinner than FC-­‐PoP

– Can enable a low-­‐profile PoP solution as large as 15x15mm

TechSearch 2

An interesting comparison of Amkor’s SWIFT vs ASE’s FOCoS vs TSMC’s InFO.

techsearch 3

Lastly, the TechSearch list of fan-out WLP evolving applications:

  • Baseband processors
  • Application processors
  • RF transceivers, switches, etc.
  • Power management integrated circuits (PMIC)
  • ConnecDvity modules
  • Radar modules (77GHz) for automotive plus other ADAS applications
  • Audio CODECs
  • Microcontrollers
  • Logic + memory for data centers and cloud servers
  • Power devices
  • Fingerprint sensors

Yole Developpement

Jérôme Azémar of Yole gave their take on “Fan-Out Packaging Technologies and Markets”.

Long time IFTLE readers know that we dislike the term fan out since all packages except fan-in WLP are fan out packages. To add to this Yole has added the following:

yole 1

Their take on applications is show below plotting package size vs IO count.

yole 2

Yole sees significant future growth initiated by the Apple adoption of the TSMC InFO package.

yole 3

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 355 iPhone 8 Teardown; NHanced Semi; Morris Chang to Retire

By Dr. Phil Garrou, Contributing Editor

iPhone 8 Teardown

TechInsights has begun their teardown of the iPhone 8. [link]

Pics of the main board are shown below.

TechInsights

 

techinsights 2-2 TechInsights 1-2

– The AP (application processor) is in a Package on Package (PoP) with Micron 3GB Mobile LPDDR4 SDRAM.

– The biggest new feature of the AP at announcement is a dedicated “Neural Engine” primarily for Face recognition.

– The video performance is claimed to be the highest quality video capture available in a smartphone. The AP features an Apple-designed video encoder enabling 4K video at 60 fps and Slo-mo 1080p video at 240 fps.

– For we packaging aficionados, the big news is the absence of TSV arrays in their CIS. Preliminary analysis of the die photo suggests to TechInsights that it’s a Sony back-illuminated Exmor RS stacked chip from which they infer that the stack is using hybrid bonding (what Sony licensed from Ziptronix) for the first time in an Apple camera. [see IFTLE “Updating CMOS Image Sensor Technology”]

The SEMI 3D Packaging and Integration Committee

The SEMI International Standards Committee, at their SEMICON West 2017 meeting, approved the transformation of the existing 3D Stacked IC Committee and Assembly & Packaging Committee into a single, unified 3D Packaging and Integration Committee [link] with a charter to:

To explore, evaluate, discuss, and create consensus-based specifications, guidelines, test methods, and practices that, through voluntary compliance, will:

  • include the materials, piece parts, and interconnection schemes, and unique packaging assemblies that provide for the communication link between the semiconductor chip and the next level of integration, either single- or multi-chip configurations. It relates to the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, flexible electronics technology
  • promote mutual understanding and improved communication between users and suppliers, equipment, automation systems, devices, and services
  • enhance the manufacturing efficiency, capability and shorten time-to-market and reduce manufacturing cost

You can get involved with the SEMI International Standards Program at:  www.semi.org/standardsmembership.

Enhanced Semiconductor

NHanced Semiconductors Inc. was launched as a spin-off of Tezzaron Semiconductor in 2016. In the course of developing its advanced 3D memory devices Tezzaron developed technical expertise in ancillary semiconductor technologies.  While Tezzaron will continues to develop and manufacture memory devices with specific focus on its DiRAM4 products, Bob Patti, Bob Patti, past CTO of Tezzaron informed IFTLE that NHanced Semi exists to implement and expand that expertise for process development, prototyping, small volume manufacturing. “We will help determine the optimal packaging solution for customer needs.  If they need custom design work, we can do that; if their design is complete, we’ll assist with 3D or 2.5D enablement.  Sourcing, manufacture, assembly, test – we will handle the entire process from concept to completion”

NHanced Semi has recently completed the purchase of the former Morrisville NC Novati fab, the fab that used to be Ziptronix. Bob indicated that Nhanced will be doing customer R&D development projects and then passing them off to partner Novati to scale and commercialize. Nhanced has replaced tools that Novati had shipped from Morrisville to Austin and their full line in Morrisville should be operational shortly. The 24,000 square foot fabrication Morrisville, NC facility is equipped for rapid prototyping, with a focus on 2.5D and 3D integrated circuit assembly. Current equipment can perform surface prep, bonding, thinning, and pick-place on multiple wafer sizes (100mm to 200mm). NHanced is currently quoting and taking orders for 4Q activity

Speaking of Novati, a recent report from Austin indicates that they have been acquired by start-up Skorpios, a fabless semiconductor manufacturing company producing communications products. [link]

Morris Chang announces retirement

ChangWhen a wise man speaks it is best to listen. Certainly we must all agree that Morris Chang, the “father of Taiwans chip industry,” who has led TSMC, for 30 some years, is a wise man. Long time IFTLE readers will recall my encounter with Chang in the late 1990’s when I was visiting TSMC introducing materials for bumping. He personally attended this low level meeting telling me “I need to better understand this bumping technology…so teach me”

Well, Morris Chang, 86, has announced that he will retire in June, after having built the world’s biggest foundry chipmaker [link].

Earlier this summer, this wise man was quoted as saying “Packaging can extend physical limits of semiconductors…” [link]

Chang identified the impact of packaging on high-performance computing applications such as AI and deep learning, graphics processors, augmented reality (AR) and virtual reality (VR) applications which he feels will drive future IC market growth.

We are all aware that TSMC has developed a new generation of packaging , its integrated fan-out (InFO) wafer-level packaging (WLP) technology and has recently expanded its chip-on-wafer-on-substrate 2.5D (CoWoS) technology to the fabrication of 16nm chips, and offered second-generation High-Bandwidth Memory (HBM2) and a GPU modules to support artificial intelligence (AI), deep learning and other high-performance computing applications.

When a wise man speaks, it is best to listen!

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 354 The Case for µLED Displays

By Dr. Phil Garrou, Contributing Editor

AntmanIt is true, as Shakespeare one said, that “A Rose by any other name would smell as sweet” but … in our times, it is important to have an unambiguous name that clearly indicates what you are talking about. Unfortunately, this is not the case for micro LED displays (µLED Displays). There are those for which this term brings to mind a millennial trying to read the Wall Street Journal on his smart watch with a magnifying glass or possibly a display worn by the Astonishing Antman.

The problem obviously is the grammatical issue of what the µ modifies…i.e. a micro (LED display) or a (micro LED) display. While it may be fun to consider how to create a display for the Antman, we will be talking about the latter. IFTLE thought a primer on the subject was in order since this technology has become more and more dependent on interconnect and assembly technologies being supplied by the packaging community.

IFTLE certainly considers this a “futures” technology, meaning still a few years out, but always remember “…the leading edge is where the money is made!”

Comparing the Display Technologies

TFT LCD (thin film transistor liquid crystal displays) were being developed in the 1970s, but by the late 1980s it was publically thought to be way too difficult to yield (“.. you cannot have bad pixels on a TV set”) and certainly a much too expensive a technology to ever displace the cathode ray tubes used for TV and desktop computer displays. Well we all know what happened next and clearly without that technology transformation there would be no laptops or smartphones or smart watches today.

Next on the time line came OLED developed initially by Eastman Kodak in the late 1980s. An organic light-emitting diode (OLED) is a LED in which the emissive layer is a film of organic compound that emits light in response to an electric current. This layer is sandwiched between two electrodes (typically the upper electrode is transparent such as ITO). An OLED display works without a backlight, and is thinner and lighter than a LCD. OLEDs have traditionally been expensive to manufacture and only LG and Samsung made them. Samsung has been working in OLED devices for a decade and is currently using the technology in their smart phones and televisions. Today, the cost has come down dramatically, and now OLED TVs are very affordable. Apple began using OLED displays in its watches in 2015 and in its laptops in 2016.

The term “Micro-LED” was first used by Cree in its US patent “Micro- led arrays with enhanced light extraction” in 2001. The patent describes arrays of interconnected LEDs with individual sizes of less than 30μm.

While there currently are no µLED displays in production, the companies developing the technology believe that it has the potential to challenge OLED and LCDs in the future. Like OLED, it does not require a backlight, producing light in each individual pixel. µLED have the advantage of lower power consumption, higher brightness, ultra-high definition, high color saturation, faster response rate, longer lifetimes and higher efficiencies compared to LCDs and OLEDs.

The three technologies are compared in cross section in the figure below [link]

led 4

 

µLEDs were placed onto the industry technology roadmap 2 years ago following Apple’s acquisition of LuxVue, which claimed that its technology was 9x brighter than OLED and LCD. Then Oculus (Facebook) acquired InfiniLED another µLED company which claimed “… a 20 – 40X reduction in power consumption” [link].

In most cases, the µLED chips are manufactured separately then positioned and connected to the transistor matrix via a pick and place process show in the figure below.

LED 1

Singulation of μLED display chips is typically achieved by bonding the epi wafer to a carrier and plasma etching in the die streets. According to Yole Developpement LEDs as small as 5μm have been demonstrated, but applications requiring >1500 PPI (pixels per inch) might require even smaller sizes.

led 5

 

Traditional pick and place equipment cannot pick up such small dies. Such tools typically have throughput around 25,000 places per hour. If large displays are to incorporate millions of tiny LEDs they cannot be assembled by such a method. Thus a requirement for µLED displays is a massively parallel pick and place technology. Players who have developed such technology include Luxvue and X-Celeprint who we have discussed on IFTLE before [see IFTLE 203, “Apple Acquires LuxVue µ-assembly Technology”]

X-Celeprint has developed MEMS-like sacrificial release processes for LED chips. Luxvue uses an electrostatic technology for their massively parallel pick-up, while Xceleprint uses an elastomeric stamp.

The µLED display concept was first validated by Sony in 2012 [link]. Their 55 inch “Crystal LED TV“ which utilized 6MM tiny LEDs (2 million each for red, green, blue subpixels) to reproduce a picture in Full HD resolution. Sony claimed that it had 3.5 times the contrast ratio, 1.4X the color range, and 10X faster response time compared to a traditional LCD.

HVM at costs acceptable to the proposed applications still faces significant engineering and manufacturing challenges. Most expect to see smart watches, being worked on now, as the first application to reach commercialization in the next few years with Apple in the lead. The drivers for this application include battery life and display brightness.

µLED performance and supply chain players are compared below [link].

led 2

While it will likely take considerable time, effort and investment to establish an HVM infrastructure, µLED could emerge as an alternative to OLED in the future as LCD fades away.

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