Insights From Leading Edge

IFTLE 308 SEMICON Taiwan Part 2: Laser Processing for WLP; IoT in the Post-Smart Phone Era

By Dr. Phil Garrou, Contributing Editor

Continuing our look at Advanced Packaging in SEMICON Taiwan 2016.

AMKOR – Lasers for the Manufacture of WLCSP

WL Huang of Amkor examined the use of lasers in the manufacture of WLCSP (fan-in WLP). As we all know by now Huang pointed to size, weight, cost and performance as the drivers for WLCSP.

In the following chart, Huang shows that the same 7.6 x 7.6mm chip with 28 I/O saves a lot of real estate when packaged in a WLCSP and that the bulk of such fan in WLP are projected to be for analog and mixed signal devices.

amkor 1

The main applications for laser in WLP are:

Laser marking

  • Scribe product info on die backside for traceability

–Laser dicing

  • Separate product from wafer form to die form

–Advanced process node low-k wafer (90 nm and below). Delamination can be easy observed by blade saw due to low-k material being more brittle

–Saw street design issues – reduce topside chipping and peeling

–Saw street width shrink – By shrinking saw street width, gross die per wafer would be increased which can reduce unit cost, ex. RF switch, LNA products

amkor 2

Two kinds of laser cut can support saw street width down to 20 μm: Stealth dicing (SD) and full laser cut.

The stealth dicing process is shown below:

amkor 3

The key to full laser cutting is minimizing the HAZ (heat affected zone).

Amkor 4

ITRI – Emerging Trends & Apps for IoT

Ray Yang of ITRI examined the “Emerging Trends and Applications of IoT in the Post Smart Phone Era”. This presentation started with two interesting slides depicting Taiwan’s electronics revenue.

2014 Semi industry ranked first in value-added among Taiwan’s manufacturing sectors. The foundry business contributes the most to the Taiwan IC industry as shown in the breakout below.


Taiwan IC packaging and test accounts for more than half of worldwide assembly and test revenues.


When examining the future of autonomous vehicles he broke out the requirements into the 3 functions: sensing, understanding and action as shown below.


For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 307 Micross Acquires RTI Int Fab & Personnel ; Teledyne Heterogeneous Integration with Ziptronix DBI; Semicon Taiwan part 1: Market Trends

By Dr. Phil Garrou, Contributing Editor

Micross Components Acquires RTI Int. Fab and Packaging Group

Micross Components of Orlando, FLA announced the acquisition of RTI International’s Microsystem Integration and Packaging group and fab in Research Triangle Park, NC. Some of you may recall this RTI site as The Microelectronics Center of NC (MCNC) in the late 19080s through early 2000’s.

Micross is a provider of bare die and wafers, custom packaging and assembly, component modification services, electrical and environmental testing to manufacturers and users of semiconductor devices. The 35 year old company serves the Defense, Space, Medical, Industrial, and Fabless Semiconductor markets.

This acquisition brings the RTI wafer bumping, 2.5D/3D packaging and interconnects technologies to the hi-reliability electronics platform of Micross. Micross plan is to expand its capabilities to serve customers in the defense and medical electronics sectors with these newly acquired advanced packaging technologies.

The Micross “Advanced Interconnect Technology” ( AIT )” team will be led by VP Dr. John Lannon , Director of Operations Rex Anderson and Director of Engineering Alan Huffman.

The financial details of the acquisition were not revealed.

Teledyne Details Heterogeneous Integration using Ziptronix DBI

In IFTLE 303, we indicated that Sony was using the Ziptronix DBI process in their image sensors for the Samsung Galaxy S7 [link]

We have recently discovered that Teledyne, under the DARPA DAHI program, has demonstrated 3D integration of high- performance compound semiconductor devices and Si CMOS using similar technology. Teledyne’s Miguel Urteaga indicates that “… Adding the complexity and integration density of CMOS to Teledyne’s ultra-high speed Indium Phosphide bipolar transistor process enables new classes of mm-wave and sub-mm-wave electronics for future DoD and commercial applications” A cross-section is shown below.



Over the next few weeks we will review some of the highlights of the recent Semicon Taiwan Conference. This week we will look at the “market trends” forum moderated by Elizabeth Sun of TSMC.

Handel Jones – Int Business Strategies 

IBS projects the Semiconductor market to decline in 2016. He market broken out by product type is shown below:



IBS projects that 3D NAND flash will overtake 2D NAND Flash in 2018. 64 layers should be in volume production in 2017. Samsung appears 12-18 mo ahead of its competition.



Wafer fab activity in China shows a strong emphasis on memory as shown below. However Chinese DRAM vendors are not expected to have a large impact on supply before 2020.


Dan Tracy – SEMI Equipment & Materials Outlook

Of the 21 fabs beginning construction, 11 will be in China.


200mm capacity is expanding with 8% growth expected between 2015 and 2019.

The wafer materials forecast is shown below:


The packaging materials forecast is shown below. “Other” includes solder balls and WLP dielectrics.


A key factor here is that laminate based substrates will begin to feel the pressure of FOWLP packaging as they take market share.  

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 306 Qualcomm Acquisition of NXP?; HBM IP at Open Silicon; IEEE 3DIC Program

By Dr. Phil Garrou, Contributing Editor

Qualcomm Negotiating to Acquire NXP

Long time readers know that IFTLE has been following the consolidation in our industry for more than 8 years now based on the basic laws of economics telling us this was going to happen. [see IFTLE 241 “Simply Obeying the Laws of Economics”]

Reports from multiple financial sources indicate that NXP Semiconductors has hired an investment bank to help them deal with recent acquisition offers. Qualcomm is viewed as the likely acquirer. According to the Wall Street Journal (WSJ) the deal would be worth over $30B. [link]

Qualcomm and NXP both supply Apple. Qualcomm apparently has its eye on NXP’s position in the automotive supplier business based on its Freescale takeover in 2015. The automotive chip business will reportedly show above average future growth.



Bloomberg reports that others who could possibly jump in with bids includes Broadcom, Intel and Samsung [link].

According to the WSJ, the deal would reshape Qualcomm. While Qualcomm currently derives most of its revenue from designing and selling chips, the company earns more than half of its profits from licensing its wireless patents to nearly all makers of mobile phones.

HBM IP at Open Silicon

TSMC’s Open Innovation Platform (OIP) Forum was held Sept. 22nd at the Santa Clara Convention Center.

A recent discussion on Semiwiki [link] by Tom Simon indicated that Open Silicon discussed their IP for HBM memory stacks on 2.5D interposers at the meeting.

This topic is discussed in detail on the Open Silicon web page [link].

Open-Silicon’s subsystem IP solution comprises the HBM Controller, PHY and 2.5D interposer IO addressing interoperability and 2.5D design, test and SiP packaging challenges. The HBM IP claims to be suitable for graphics, high-performance computing, high-end networking and communication applications that require low power and small form factor.

Open SI 1

Open-Silicon claims their HBM IP is the industry’s first solution for integrating HBM into ASICs for high performance and low power. By integrating the HBM protocol controller, PHY and IO into one sub-system IP product, interoperability aspects between the different system components are addressed. The Open-Silicon HBM IP fully complies with the HBM-Gen2 (2 Gbps per signal) JEDEC standard.

Back to the OIP presentation, Simon reports that Open-Silicon has implemented an HBM reference design in 16nm. According to Open Silicon 16 nm FinFET is the key to unlocking the full benefits of HBM since it can potentially reduce power and boost performance by 50% relative to 28 nm.

In the current design Open Silicon replaced (24) DDR3 1600 with 1 HBM stack, the power consumption went from 1.0 mW /Gbit to 0.33 mW. The data rate climbed from 4 GB/s up to 256 GB/s.

OpenSi 2

To effectively shield the 0.85 um signal lines from cross talk, ground wires of 0.5um were placed 2.1um to the side of each signal wire. This left 2.1 um for each signal line.

IEEE 3DIC Conference


ieee 3dic


The IEEE 3DIC conference, which I helped put together several years ago, is back in SF this year and will be held Nov 9 – 11th. [link]

Topics will include:

– 3DIC Processing                            – Design and Applications

– Thermal Analysis                           – Bonding

– Reliability and Stress                  – Power & Signal Integrity


Next week we will start our coverage of SEMICON Taiwan packaging activities. For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 305 Where is Samsung Widecon?? ; TSMC InFO found in iPhone 7

By Dr. Phil Garrou, Contributing Editor

Samsung Widecon Technology

Samsung introduced us to their Widecon technology in 2014 [link] and it was predicted that this 3D TSV technology linking memory to processor would be introduced in the Exnos 6 generation.



Dick James (Chipworks) recent assessment of the tear own of the Galaxy note 7 [link] tells us that

the application processor that drives this phone is the Exynos 8 Octa (Exynos 8890), similar to the Galaxy S7 and S7 edge. It has an eight-core CPU, with four Samsung designed cores that can run at 2.3 GHz, and four ARM Cortex A53 cores operating at up to 1.6 GHz. Stacked on top of the CPU in the usual package-on-package (PoP) stack, is 4 GB of Samsung LPDDR4 SDRAM. Now that we have 20 nm DRAM processes, the dies are small enough that they are packaged in a 2 x 2 x 2 configuration. The four stacks of two 4-Gb memory dies are mirror-imaged, on both the vertical and horizontal axes.

exnos 8

So – it looks like we are still going to have to wait for the commercial introduction of widecon.

TSMC InFO becomes commercial reality

For several years ow, rumors have been rampant that TSMC scaling of their InFO packaging technology was focused on acessing the highly lucrative Apple iPhone market. For instance see IFTLE 283 “Will Packaging make the Difference for TSMC?”


While a definitive process flow for InFO has not been publically described by TSMC, in IFTLE 261 we reported on a rumored InFO process flow which consists of (1) copper pillar plating on the die, (2) die placed face up on tape, (3)molding to generate reconstituted wafer, (4) polish down to reveal tops of pillars, (5) RDL processing on this polished surface. The capability for finer features than standard fan out packaging reportedly comes from the more planar starting surfaces and better control of the photo processes.

We have also pointed out rumors that ASE would second source an InFO process [see IFTLE 292]

Now a Chipworks teardown confirms the presence of the A10 Fusion chip, manufactured by TSMC with a reported 3.3 billion transistors, in the iPhone 7 link]. Chipworks confirms that the process is a TSMC 16nm finfet based.

Apple A10

“The A10 sits below the Samsung K3RG1G10CM 2-GB LPDDR4 memory. This is similar to the low power mobile DRAM as the one we found in the iPhone 6s. Looking at the X-rays we see the four dies are not stacked, but are spread out across the package. This arrangement keeps the overall package height to a minimum. Assembled in a package-on-package assembly with the A10 InFO packaging technique reduces the total height of PoP significantly”

So the InFO rumors were in fact correct and this in turn will fuel the drive towards HVM of fan out packaging.

ASE Providing SiP for Apple

We had previously noted that ASE was the sole supplier for Apple’s custom-designed SiP modules for used in the Apple Watch. [See IFTLE 238 “ASE & the Apple watch, …”]

Digitimes now reports that ASE, through its Shanghai-based subsidiary Universal Scientific Industrial (USI), has obtained SiP orders for Wi-Fi, fingerprint sensor and force touch modules used in the recently-released iPhone 7 [link].

ASE holds a nearly 80% stake in USI, which has been engaged in backend services for SiP modules.

For all the latest information on Advanced Packaging, stay linked to IFTLE…


IFTLE 304 Renesas Acquires Intersil; Intel’s Knights Landing: An Update

By Dr. Phil Garrou, Contributing Editor

Renesas Acquires Intersil

Consolidation continues with the latest deal announcement of Renesas buying Intersil for $3.2B beating out Maxim who was known to be seeking a similar deal [link]. Renesas reportedly aims to complete the deal by June 2017. The acquisition will need to win approval from the US Committee on Foreign Investment, which scrutinizes deals for potential national security issues.

Renesas was created in 2003 from the chip-making units of NEC, Mitsubishi Electric and Hitachi . It is the world’s largest auto semiconductor maker in 2014,[ one of the world’s largest makers of semiconductor systems for mobile phones, the world’s largest maker of microcontrollers 9 controls nearly 40 percent of the global market for microcontroller chips used in automobiles), and the second largest maker of application processors. Its automotive and industrial businesses accounted for 70% of its revenue in 2015. The combination with Intersil is expected to result in better products for in-vehicle entertainment, battery management and safety systems [link].

Intersil, headquartered in Milpitis CA, formed in 1999 when Harris Corp spun off its semiconductor business. In 2014 it had ~1000 employees and revenue of $562MM. It is known for power management ICs and precision analog technology for applications in industrial, infrastructure, mobile, automotive and aerospace. The company supplies power IC solutions including battery management, computing power, display power, regulators a d controllers and power modules; as well as precision analog components such as amplifiers and buffers, proximity and light sensors, data converters, timing products, optoelectronics and interface products. They are a major supplier to the military and aerospace industries

Intel Knights Landing

We first discussed Intel’s Knights Landing in IFTLE 198 [link].

The Knights Landing (KNL) chip is the first commercial processor with very high bandwidth MCDRAM memory (Intel’s name for Microns HMC memory cubes) right next to the CPU in the same package, and the first integrated high speed main memory on any class of Xeon processor. Intel is now apparently able to ship Knights Landing processors in volume with the announcement that they will be shipping several variants of the Knights Landing X86 processor starting September 2016.

Intel disclosed he memory hierarchy of Knights Landing last year, explaining how the mix of local MCDRAM on the Knights Landing package and DDR4 memory that is on the motherboard (but controlled from on-chip memory controllers) like regular servers can be used in different ways, depending on the workload.

Intel 2

The performance jump from the Knights Corner coprocessors to the Knights Landing processors ranges from somewhere between 2.6X and 2.9X with the price only rising by 1.4X to 1.5X.

Intel expects to ship more than 100,000 Xeon Phi units this year into the HPC market. More than 30 system makers are reportedly going to use these Knights Landing processors [link].

Intel is clearly taking as little more time to ramp up the yields on the 14 nanometer processes used to etch the latest Xeon Phi chips, and given that at more than 8 billion transistors per die, it is also the largest chip that Intel has ever made.

intel 1

300mm KNL Wafer

Hynix Building up CMOS Image Sensor Capability

Our discussions in IFTLE 303 on the status of CMOS Image sensor technology had little to say about SK Hynix.

Recent reports from Korea indicate that SK Hynix is going to mass-produce their 13 MM pixel CIS at their 300mm factory M10 in Icheon Korea, in 2017. Because of the size of this CIS, it is believed that SK Hynix could not manufacture at a profit at 200mm. [link]

In October of 2007 Hynix entered the CIS business. In 2008 Hynix acquired Siliconfile, a CIS fabless manufacturing company. Until now, SK Hynix had been supplying CIS with < 5MM pixels.To increase profitability, it has been attempting to increase the percentage of 8MM pixel products to Samsung, Huawei, LG, and other Smartphone manufacturers for their low and medium priced Smartphones.

According to TSR (Techno Systems Res) total sales from global CIS markets in 2015 were about $9.2B. SK Hynix market share of 3.7% stands 6th behind Sony (44.8%), Samsung Electronics (16.5%), OmniVision (13.2%) ON Semi (Aptina Imaging, 6.1%) and Canon (5.3%).

Reader Input on Lester the Lightbulb ( i.e. the Govt. forcing Incandescent technology out of the market )


After reading IFTLE 300 a reader sent in the following picture he took at a Chinese restaurant in Portland Maine.

The lighting fixture over one of the tables seemed rather dim and on further investigation he found two burned out compact florescents (CFL) and an incandescent burning brightly. Certainly, we do not know when any of the bulbs were inserted into the fixture, but after reading IFTLE 300 the reader said this made him laugh out loud or as the younger folks say LOL.

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 303 Sony Introduces Ziptronix DBI Technology in Samsung Galaxy S7

By Dr. Phil Garrou, Contributing Editor

It has been awhile since we last checked in on the CMOS Image sensor (CIS) community to see what the latest advances in packaging were [see IFLE 172 [link], 244 [link], 272 [link] and 278 [link].

For those that need to catch up on the technology roadmap, Toshiba was the first to commercially implement CMOS image sensors with backside TSV last technologies in 2007 ( this was covered thoroughly by my predecessor blog PFTLE which was unfortunately scrubbed from the internet when “Semiconductor International “ went out of business. This technology is well explained by CEA Leti [link].

Many of us stated in 2007 that further advances could be obtained by removing the CMOS circuitry to a separate layer and forming a true 3D chip stack, but the technology implementation had to wait while the industry first converted to back side imaging technology.

“Backside Imaging” – BSI

With a conventional front-illumination structure, the metal wiring above the sensor’s photo-diodes impede photon gathering. A back-illuminated structure (figure below) increases the amount of light that enters each pixel due to the lack of obstacles such as metal wiring and transistors that have been moved to the reverse of the silicon substrate [link].

Back side illumination


Back Side Imaging – stacked

The next generation, as expected, combined both BSI and stacking. Conventional CMOS image sensor technology creates the pixel function and analog logic circuitry on the same chip. The motivations for stacked chip CIS include: optimization of each function in the stack, adding functionality to the stack and decreasing form factor.

Since the pixel section and circuit section are formed as independent chips, each function can be separately optimized, enabling the pixel section to deliver higher image quality while the circuit section can be specialized for higher functionality. In addition, faster signal processing and lower power consumption can also be achieved through the use of leading process for the chip containing the circuits.[link]



So, where do things stand commercially?

The 2014 image sensor market was estimated by Techno Systems Research as shown below.




Sony is clearly leading in commercializing the latest CIS packaging technologies.

In 2012 Sony announced the Exmor RS, Stacked CMOS back-side illuminated sensor, where the supporting circuitry is moved below the active pixel section, giving ~ 30% improvement to light capturing capability [link 1] [link 2].

The first generation Sony BSI-Stacked chips employed via-last TSVs to connect pads from the Sony-fabricated, 90 nm generation CIS die to landing pads on a Sony-fabricated, 65 nm generation ISP. The die stack was partitioned such that most of the functionality of a conventional system-on-chip (SoC) CIS was implemented on the ISP die; the CIS die retained the active pixel array, final stage of the row drivers, and comparator portion of the column-parallel ADCs

Some of the biggest names in tech use Sony sensors: The iPhone 6 camera has a Sony sensor, as does the Samsung Galaxy S6, Motorola phones, Nikon DSLRs, and Olympus mirrorless cameras. [link]

Earlier in 2016 it was reported that there are two versions of the Samsung Galaxy S7. One has a Samsung stacked ISOCELL sensor (S5K2L1) and the other a special Sony stacked sensor (IMX260) [link].

The recent Chipworks teardown of the Samsung Galaxy S7 with a Sony IMX 260 revealed BSI stacked technology [link 1]. Furthermore it revealed the first reported use of the Ziptronix (now Tessera) Direct Bond interconnect (DBI) technology rather than prior oxide –oxide bonding with subsequent TSVs connecting through the oxide interface [link 2]. This BSI-stacked DBI technology is possibly the next step in the CIS roadmap.

The Chipworks cross-section (see below) reveals a 5 metal (Cu) CMOS image sensor (CIS) die and a 7 metal (6 Cu + 1 Al) image signal processor (ISP) die.  The Cu-Cu vias are 3.0 µm wide and have a 14 µm pitch in the peripheral regions.  In the active pixel array they are also 3.0 µm wide, but have a pitch of 6.0 µm. Note that in the images we’ve included we do see connections from the Cu-Cu via pads to both CIS and ISP landing pads.

Sony DBI



Omnivision was the first to sample BSI in 2007 but costs were too high and adoption was thus very low.

In 2015 Omnivision announced their OV 16880 a 16-megapixel image sensor built on OmniVision’s PureCel-S™ stacked die technology [link].


Samsung’s first entrant into stacked technology with TSV was also at 16MP with the Samsung S5K3P3SX in late 2014. The CIS die is face-to-face bonded to a 65nm Samsung image signal processor die and connected with W based TSV. The CIS die is fabricated on a 65nm CMOS process with 5 levels of interconnect as shown below, courtesy Chipworks.


ON Semi (Aptina)

In early 2015 On Semiconductor (Aptina) introduced its first stacked CMOS sensor the AR 1335 with 1.1µm pixels. It resulted in a smaller die footprint, higher pixel performance and better power consumption compared to their traditional monolithic non-stacked designs. They announced that it would be introduced in commercial products in late 2015. [link]


In late 215 Olympus announced the OL 20150702-1 a new 3D stacked 16MP CMOS image sensor [link]

For all the latest on Advanced IC Packaging, stay linked to IFTLE…

IFTLE 302 Amkor Denies Takeover Rumors: BCB Team Wins Amer. Chem. Soc. Award; IMEC’s Beyne Reviews Via-Middle TSV Technology

By Dr. Phil Garrou, Contributing Editor

Amkor Denying Takeover Rumors

Amkor finds itself denying rumors published in Digitimes that there is a takeover bid from Chinas Nantong Fujitsu [link]. If true, Nantong Fujitsu would become the largest OSAT in China as well as the second largest in the world, trailing only ASE.

Taiwan’s Central News Agency has also reported that there is speculation that Nantong wants to buy Amkor [link]

Nantong Fujitsu Microelectronics Co., provides IC assembling and testing services to the semiconductor industry in China. The company offers DIP, SOP; BGS, FC and WLP for automotive devices, memory products, analog ICs, microcontrollers, wireless/RF and analog devices; portable products such as cell phones, data storage systems, notebook computers, and pagers.

Nantong Fujitsu acquired an 85% share of AMDs Penang Malasia and Suzhou China packaging facilities for $371 MM earlier in 2016. [link]

Although Amkor is denying the rumor, such an offer would fit with he previously discussed China 2020 plan to become a major player in packaging [ see IFTLE 296 “…China the Wild Card…” ]

BCB Team Wins American Chemical Society (ACS) Award

The American Chemical Society (ACS) has just announced that a team of current and ex-employees of Dow Chemical have been awarded the ACS award for team innovation for their development and commercialization of Benzocyclobutene (BCB) dielectric [link].

The team, which consisted of Phil Garrou (yours truly), Bob DeVries, Carol Mohler, Eric Moyer and Ted Stokich, worked together to define and scale up a commercial product from a Central Research curiosity.

The award is for work done some 25 years ago, when the Dow team, partially under a DARPA contract, developed a photosensitive BCB formulation which was incorporated into the bumping and wafer level packaging processes developed by FCT (Flip Chip Technologies – Ultra CSP) ) and Unitive (Extreme CSP) and later licensed and practiced by most of the major Taiwan and Korean OSAT houses. At the time, current generations of PI failed to produce manufacturable processes and in the early 2000’s, before new generations of PI and PBO were developed to meet these needs, BCB based components were being used in nearly every cell phone produced in the world.

BCB also revolutionized the MANTECH defense industry by allowing Triquint, Teledyne, NGAS, Raytheon, MA-COM and many others develop multilayer interconnect for their GaAs, GaN and InP processes [link].


For those that are interested the history of BCB was summarized in the article “Development and Commercialization of BCB for Microelectronic Applications” by Garrou et. al., in The World of Electronic Packaging and System Integration , B. Michel and R. Aschenbrenner Eds., ISBN 3-932434-76-5. 


In the July issue of IEEE Trans. CPMT (p. 983) IMEC’s Eric Beyne reviewed via middle TSV technology development [link].

This paper discusses the key technological aspects of via-middle Cu TSVs, The 3-D integration concept and the wafer front and backside process technology for a 5μm x 50μm Si TSV. A very nice review of TSV formation, exposure and the impact of TSVs on devices.

The via-middle process flow consists of two main modules: 1) the via-middle process between FEOL and BEOL processing and 2) the backside thinning and via reveal process.

Via Middle Process

The via-middle TSV process consists of integrating the TSV module between the end of the FEOL process (typically the formation of W contact metal to devices) and the first damascene Cu interconnect layers. The thermal limitation for processing is, therefore, in the range of 420 –450°C.

The IMEC baseline TSV is a 5-μm diameter, 50-μm deep Si etched TSV. The oxide liner is deposited using a TEOS/O3 pulsed CVD process with a target thickness of 200 nm at the TSV bottom.

As a Cu diffusion barrier layer, 5nm PVD Ta is used. As PVD is highly non conformal, this requires a 120–140nm thick Ta layer on the frontside of the wafer. Cu PVD is used as a Cu seed plating layer. To achieve a sufficiently thick Cu seed at the bottom of the via, an 800–1000nm thick Cu PVD deposit is required on the wafer surface area. This seed layer allows for Cu electrochemical deposition (ECD) and voidless filling of the vias.

After filling a 5 × 50μm via, the thickness of Cu deposited on the wafer surface is 3μm. The actual copper diameter is ∼4.9μm at the top and 4.3μm at the bottom of the TSV. To stabilize the Cu in the TSV and remove impurities after plating, a high temperature anneal is performed before Cu CMP resulting in Cu grain growth and a stable Cu microstructure. Finally, CMP is used to remove the Cu overburden, the Ta barrier layer, and the oxide liner.

IMEC process flow

The main challenge for scaled TSVs is, however, the deposition of a Cu diffusion barrier layer and a Cu electroplating seed layer.

Fully conformal plasma enhanced ALD oxides offer a clear advantage when scaling the TSV diameter. In addition, these dielectrics reduce the thickness of the oxide deposited on the wafer surface by 50%, greatly reducing the oxide liner CMP process time.

As the aspect ratio of the TSVs increases with diameter scaling, the use of PVD for barrier/seed deposition becomes more difficult. ALD deposited barriers are shown to be highly effective for scaled TSV since they can reduce the overall TSV process costs by reducing the deposited layer thickness on the wafer surface by ~10× and, therefore, reduce the CMP time.

Wafer Backside Flow

The Si wafer has to be thinned to enable backside contact to the embedded via middle TSV structures. This requires temporary bonding of the TSV wafer on a carrier substrate, wafer thinning, and a TSV via-reveal process.

Wafer thinning is performed by mechanical wafer grinding. Mechanical thinning results in backside silicon damage, stress, cracks, and dislocations therefore, after grinding and wafer cleaning some of

the backside Si is further thinned using either wet or dry methods. After slightly recessing the Si surface with respect to the backside revealed TSV, the oxide liner is still present on the top of the exposed TSVs. In order to avoid possible backside Cu contamination on the thin Si wafer, a backside SiO/SiN passivation layer is deposited. This has to be performed at relatively low temperatures (<200 °C) as the thin wafer is supported by a temporary carrier using a polymeric glue material.

A backside CMP process step exposes the Cu of the TSVs for further backside processing (e.g., metal redistribution, solder microbumps, and so on).

For all the latest in Advanced Packaging, stay linked to IFTLE…


IFTLE 301 Are Silicon Circuit Boards in our Future?

By Dr. Phil Garrou, Contributing Editor

In IFTLE 300, we commented that the imminent end to scaling will force changes in how we approach the development of new integrated circuits and systems.

IyerSubramanian Iyer, ex IBM fellow, retired from IBM when the chip business was sold off to Global Foundries. He is now the Distinguished Chancellor’s Professor in the EE Dept. at UCLA and Director of the Center of Heterogeneous Integration and Performance Scaling (or CHIPS for short). The CHIPS mission is to interpret and implement Moore’s Law to include all aspects of heterogeneous systems and develop architectures, methodologies, designs, components, materials and manufacturable integration schemes that will shrink system footprint and improve power and performance. Let’s look at his concept of for where the industry should be going.

In the July 2016 issue of IEEE Trans on CPMT, Iyer put pen to paper ( or should we say “fingers to keyboard”) and has laid out the master plan for CHIPS in his article “Heterogeneous Integration for Performance and Scaling.”

Iyer contends that Moore’s law has so far relied on the aggressive scaling of CMOS silicon features. This in turn resulted in a dynamic system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. While scaling on chip has increased >1000X, the integration of multiple dies on packages and boards has scaled by a factor of 3 – 5X. The current slowing of semiconductor scaling [discussed in IFTLE 300] will bring a focus on heterogeneous integration and system-level scaling. This transformation is already under way with 3-D stacking of dies and will evolve to make heterogeneous integration the backbone of sustaining Moore’s law in the years ahead.

While the SoC approach has moved us forwards, a single chip does not make a system. In order to build a system, multiple chips such as processors, memory chips, field programmable gate arrays (FPGAs), transceivers, power regulators, and so on need to be interconnected. Traditionally, this has been done using a printed circuit board (PCB).

Chips are typically packaged before being mounted on the board. While it is true that the package connects the chip to the rest of the system, it does so very inefficiently. For instance, contacted gate pitches in the 14-nm node are about 40 nm, through the hierarchical wiring system, we increase that pitch up step-by-step until, at the upper most wiring level, it is a few micrometers. The C4 bumps then increase this pitch to about 150 μm. The BGA connections to the board take this further to 400 – 600 μm. In essence, to connect two chips the interconnections of chip 1 must fan out to a PCB board pitch and then fan back in to chip 2 pitch , thus causing the inefficiency . Silicon has scaled by over a factor of 1000 in the last 50 years, while packages and boards have scaled by at most a factor of 5.

Iyer contends that with increasing demands on the BW between the chips and the inability to increase the number of physical connections between the chips, serial links need to operate individually at higher and higher data rates. These higher rates mean higher frequency signals carried by the traces on the board and significantly larger noise levels and cross talk between adjacent channels. Consequences of this include:

1) The power to transmit higher frequency signals through SerDes goes up exponentially with data rate.

2) The SerDes circuits themselves become more complex to design and take up more area. modern SoCs may sometime devote almost 25% of their area to SerDes, and in some cases, an even greater fraction of chip power is allocated to SerDes function.

Approaches to System Scaling and Heterogeneous Integration

Iyer proposes Eliminating the Package and directly bonding multiple bare dies to an interconnect fabric (IF) made of silicon. He notes that the first steps in this direction have been silicon interposers but argues that this is not the ultimate solution since an interposer adds cost and complexity by adding an extra level to the overall package. What Iyer is proposing is “to go a step further and transform the interposer into the board”.

He proposes replacing the current epoxy glass PWB board with silicon. This silicon board would be a wafer on which have been processed several levels of fine pitch wiring with the top-most wiring level matching the top chip wire levels with landing pads of similar dimensions that can connect to other die that have been attached with precision alignment (0.5-μm overlay). He calls this wafer the silicon interconnect fabric (Si-IF). Electrical connections between the rigid flat die and the Si-IF will be made by thermal compression bonding. While technology at this fine scale is not available today, Iyer believes it possible in the near future. He believes that two features of this approach make it feasible:

1) the use of small die (a few millimeters on a side)

2) the fact that both the die and IF are made of relatively thick silicon, are flat and have matched CTEs.

Iyer contends that computing is evolving to a more heterogeneous architecture with a combination of special purpose processors, accelerators, and FPGAs which make this Si-IF integration scheme very attractive, since one can synthesize such systems from a variety of off-the-shelf components. In the case of mobile systems and the so-called IoT, heterogeneity is the key requirement. One can integrate analog components, sensors, MEMS, batteries, supercapacitors, and so on as needed. Overall, they expect that this approach will allow significant reduction in overall board footprint.

Iyer has listed the following requirements for such technology to come to pass.

1) Integrated Design System: Today, chips, packages, and boards are all designed separately and almost independently. This will need to become a lot more integrated. In addition, while, today, we do electrical, thermal, and mechanical design more or less independently, these three views of the system will also have been integrated.

Such a system will require significantly more understanding of the interactions between these 3 views and the development of a significantly more sophisticated set of tools.

2) New Design for Test and Repair Methodologies: As rework is no longer an option, and die-level testing will be limited in scope, the component chips will have to test themselves to a large extent. While technologies to do this exist, they will need to be adapted to bare die.

3) Interface Standardization: Our approach allows us to have a large number of inter die connections and this allows us to parallelize the connections and have simpler interfaces. However, this approach needs to be adopted universally. We believe that the standardization of slower and easier to build parallel interfaces is more easily achieved than serial interfaces.

4) Power Delivery and Thermal Management: In the case of high-end systems, one would need to deliver ∼1 kW of power at different voltages. This will require integrated power management techniques, and the use of features, such as Hi-Q inductors, buck convertors, and power switches, than can either be components attached to the IF or integrated into the Si-IF. Removing the generated heat is another challenge. One mitigating factor in the use of the Si-IF is that the silicon itself is a good thermal conductor and can be an integral part of the heat-sinking solution. The die themselves may have integrated heat sinks made, for example, with silicon fluidic channels or micro machined fins.

5) Structural Properties of Silicon: While the ability to process silicon as an IF is second to none, care must be exercised in wafer handling. Fortunately, silicon-processing equipment has evolved to accommodate this

6) Cost: It has been argued that silicon is expensive and organic materials would be more cost effective. If we need fine pitch interconnects, then in practice, material cost will be about 10% of the finished product cost. Processing the fine pitch interconnects dominates the cost. In fact, it will be very expensive to fabricate fine pitch (sub-10-μm pitch) interconnects on organic

substrates; while fully depreciated silicon fabs can do this easily and more cost effectively on silicon. There are additional benefits of silicon, such as integrated passives and active IFs. The silicon solar cell substrate suppliers have developed the so-called metallurgical grade Si that is cost competitive.

While the challenges are enormous, so too are the payoffs. When compared with the challenges and costs of continuing to shrink minimum features on a die, he believes “… the value proposition of what we have proposed here is solid”.


For all the latest in Advanced IC Packaging, stay linked to IFTLE…

IFTLE 300: ITRS 2.0 – It’s the End of the World As We Know It

By Dr. Phil Garrou, Contributing Editor

The 2015 ITRS Roadmap

The 2015 International Technology Roadmap, was released earlier this summer by the SIA (Semiconductor Industry Association). It can be accessed here [link].

If there were any practitioners left who were still denying that scaling has come to an end, this report drove a stake into their heart. No longer snickering at the “conspiracy theory”, all major organizations have now accepted the reality of a future without scaling. Even Popular Mechanics is reporting this as a major event [link].

Christopher Lee

As REM would say :

“It’s the end of the world as we know it
It’s the end of the world as we know it
It’s the end of the world as we know it, and I feel fine”

Some will still argue that the discussion has been about Moore’s Law, not scaling. They will argue that Moore’s law simply predicts a doubling of transistor density within a given integrated circuit, not the size or performance of those transistors. To me this is just semantics. First of all More’s Law is not a Law. It is an observation. Secondly, we all know that Moore’s Law and scaling, to most in our industry had become synonymous over the years.

In the recent IEEE Spectrum article “Transistors Will Stop Shrinking in 2021, Moore’s Law Roadmap Predicts” the authors note “After 2021, the report forecasts, it will no longer be economically desirable for companies to continue to shrink the dimensions of transistors in microprocessors. Instead, chip manufacturers will turn to other means of boosting density, namely turning the transistor from a horizontal to a vertical geometry and building multiple layers of circuitry, one on top of another.” [link]

In fact the ITRS changed its predictions from their 2014 report, when they said that miniaturization would continue until at least 2028. The following figure (from the IEEE Spectrum article) very clearly points out the new ITRS conclusion.

end to scaling

This will be the last ITRS roadmap put together by the Semiconductor Industry Association, which ends a 20+ year effort that began in the US and expanded to include the rest of the world. Citing “waning industry participation” which was to be expected as one after another major players stopped building fabs for the latest nodes. The technical difficulty and costs associated with leading edge fabs has resulted in significant consolidation as all readers of IFTLE are well aware. Today, there are basically just four major players left: Intel, TSMC, Samsung, and GlobalFoundries.

To some the shocker was probably IBM getting out of semi production. Back in 2009 I gave a presentation to a group of Govt officials who told me not to worry about on shore procurement because “IBM will always be around.” My response was “No, that’s incorrect; they will be out of the IC business soon because a $1B chip fab business cannot support building $5B factories.” They laughed it off and ignored the comment. I’m sure they are not laughing now!

Paolo Gargini, chair of the ITRS, astutely commented that chip buyers and designers—companies such as Apple, Google, and Qualcomm—are the ones now dictating the requirements for future chip generations, not the IDM’s that we all grew up with.

IFTLE readers know that this issue has been out there for quite awhile now, for instance at the 2015 IEEE ISSCC (International Solid-State Circuits Conference) Intel detailed results for its future 10nm manufacturing process. They stated that “10nm looks like the end of silicon scaling, to achieve 7nm, a III/V material will be required.”

Intel 1

So, where does this leave us?

The ITRS report predicts the industry will move away from FinFET ~ 2019, towards “gate-all-around transistor” technology. A few years later, transistors will use nanowires and become vertical devices. By 2024 they predict we will be facing a thermal limit which will usher in microfluidic channels to increase the effective surface area for heat transfer.

Is this all come to pass? As Yogi Berra used to say “The hardest things to predict are those that have not happened yet.”

It is clear that solutions being predicted by the ITRS front end experts are certainly front end solutions. As a reader of IFTLE you know that I have been predicting a period of increased focus in packaging. The heretofore front end equipment companies and IC fabs like TSMC, UMC and Global have certainly bought into this theory as 2.5D, 3D, fan in and fan out have become their new buzz words.

So this explains why the REM song fits how I feel now. It may be the end of the world as we have known it…but I feel fine because packaging is now, assuming it’s new position on the forefront or microelectronics. Now that manpower and emphasis have shifted to packaging solutions to customize products, I think we have only seen the tip of the iceberg in terms of technological innovation.

This is IFTLE 300, which means I have been sharing information and thoughts with you for 6 years. Thank you all for your continuing support of this blog.

Now, taking this opportunity to update a few things:

1) Lester the Lightbulb

For those long time readers of IFTLE still interested in my Lester the lightbulb “non scientific” lifetime testing [link] here is where we stand, exactly 5 years (Aug 2011) into our test.

Our LED bulb is still burning, but so is our 25 cent “Lester the lightbulb” incandescent bulb. Yes that is correct, the incandescent is still functioning after 5 years with approx. the same burn time and on/off cycling in the same area of the house. The big looser in all this is the compact florescent (CFL) which has burned out 3 times, that’s right this mercury containing technology (how can anyone call this green ?) is now on bulb #4. A pic of the bulb #3 burnout is shown below. It gave off a puff of white smoke that probably shortened my life due to mercury vapor inhalation. Lucky it didn’t start a fire.


2) Hannah and Maddie

Early on I told you that you would have to put up with pics of my granddaughters every “now and then” because “that’s what grandparents do.” It is now “now and then” once again.



3) The IFTLE Tag Line

Since its inception “Insights from the leading Edge” has intentionally put a lot of emphasis on 2.5 / 3D. It has been obvious that if this technology were to take root, it would be a paradigm shift in how we do packaging. IFTLE felt the community needed constant updates on were things stood. More than a decade has now gone by since the first articles appeared proposing we mainstream 3DIC with TSV. The first real products have now appeared in FPGAs, CMOS image sensors and stacked memory. It has clearly become one of the arrows in the packaging quiver. Will prices come down and its applications proliferate? Only time will tell.

Starting with IFTLE 301, my tag line will simply become “For all the latest in advanced IC packaging, stay linked to IFTLE.” IFTLE will certainly still cover advances in 2.5 / 3D although not with the special emphasis placed on these topics in the past.

How everyone has enjoyed their summer, I need to go off now and decide on content for IFTLE 301.

..…….It’s the end of the world as we know it, but I feel fine!…………….

IFTLE 299 Siliconware’s Ma Discusses Die Stacking Options for 2.5D

By Dr. Phil Garrou, Contributing Editor

Continuing our look at IEEE ECTC 2016:

Siliconware – Die Stacking and Integration Options with TSV Based Si Interposers

At the recent IEEE ECTC Conference in Las Vegas, Mike Ma of Siliconware compared various die stacking and integration options with TSV Si interposers. From his perspective there are four main stacking platforms for 2.5D IC in advanced packaging. They are shown in the figures below.

In the first method known as Chip on Chip (CoC) on substrate the silicon interposer is fully processed and then multiple active chips are stacked on the silicon interposer, followed by assembly of chip module on the substrate.

The interposer is diced and attached to a silicon carrier which is coated with temporary adhesive film. The carrier provides handling and warpage control capability, i.e. the silicon interposer warpage can reportedly be controlled to within 10um during high reflow peak temperature. After that, the top die can be sequentially attached onto interposer with flux and joined together via mass reflow then followed by an underfilling process. Then the silicon carrier is de-bonded and the individual chip module attached onto blue tape film frame and ready for substrate assembly just as usual traditional FCBGA process.

In the second method known as Chip on Substrate (CoS), the silicon interposer is fully processed with TSV, metal layers, u-bumps, Backside Via Reveal (BVR) and C4 bumps. The processed silicon interposer is then assembled on the substrate followed by assembly of the multiple active chips onto the interposer.

In CoS, the interposer, ( ~ 100um thick) is die bonded to an organic substrate followed by assembly of top multiple active chips. If the substrate warpage is opposite the interposer (interposer warped up and substrate warped down is usual) , there are risks of electrically open or short failures happened after die bonding process because C4 bump height can’t overcome the gap change between TSI and substrate during the die bonding thermal excursion. Thermal compression bonding (TCB) is used to keep a stable gap between the interposer and the substrate during the die bonding process. In addition, Non-Conductive Paste (NCP) or Anisotropic Conductive Paste (ACP) are used.

SPIL 3 CoC vs CoS

Chip on Wafer before TSI backside process (CoW_first) involves attaching the top active chips on front side micro-pads of silicon interposer before the silicon interposer backside bumping process.

After micro bump bonding, underfilling and molding the wafers are ground down to expose the chip tops. The wafers are then flipped and temporarily bonded to a support wafer, the interposer vias exposed and bumped. The modules are then de-bonded from the carrier to a tape ring. Finally, the modules are FC BGA assembled on the organic BGA substrates

In the Chip on Wafer after TSI backside process (CoW last) single or multiple top dies are attached to the interposer wafer after the interposer has been fully processed including front side u-bumps process, backside via revealing process, backside re-distribution layer and final C4 or Cu pillar bumping process.

After interposer is prepared to receive chips to top surface, it is flipped and supported on a carrier for backside reveal, RDL and bumping. It is then flipped onto a second carrier and he chips mounted, underfilled and molded as before.

SPIL 3 CoW first vs last-2

Comparing to the CoW first process with TSV, die bonding assembly portions are the same, but there are differences in the interposer fabrication. Instead of completing micro-bumps process first, RDL and PSV are implemented first and followed by UBM process. Since TSV-less platform has no interposer in its final form, the carrier can be either glass or silicon. After the carrier bonding process, instead of the usual backside reveal process, the TSV-less interposer will be partially removed by mechanical grinding followed by wet etching to completely remove silicon portion and stop on the remaining passivation layers. The passivation layer is then patterned to expose contact areas for further C4 bumps. Further assembly including the chip module on substrate processes are the same as described for CoW first.

Ma compared the chip stacking options in the chart below.

SPIL 3 Comparison of chip stack options

Editorial correction: In IFTLE 298 IFTLE inadvertently assigned credit for the “20um Pitch Thermo Compression Copper Pillar Bonding” work to IMEC instead of rightful authors at IME. This should have been corrected by now, but we did want to offer our apologies for this error.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…