Insights From Leading Edge

IFTLE 206 COSMOS and DAHI Herald the Era of 3D Heterogeneous Integration

By Dr. Phil Garrou, Contributing Editor

For about a decade now, we have been awaiting the full commercialization of 3DIC. From the beginning most practitioners laid out a roadmap where CMOS Image sensors led the way followed by memory stacks, memory-on-logic, logic on logic and lastly the holy grail of heterogeneous integration where we could combine advanced semiconductor materials and different  functions, with high-density silicon CMOS technology.

Indeed CMOS image sensors have led the way [ see IFTLE 199,  “Omnivision Roadmaps 3D stacking for CMOS Image Sensors…” ] and DRAM memory stacks from Hynix and Micron are on the verge of full commercialization [ see IFTLE 202, “ConFab 2014: Novati, Lumileds; Chipworks; IEEE CPMT Packaging Panel”].

A lesser publicized fact is that we are actually very close to functional heterogeneous integration thanks to the efforts of many participants in the DARPA sponsored COSMOS and DAHI programs.

The development of non SI based semiconductor (compound semiconductors, CS) electronics has been motivated by their superior materials properties relative to silicon. For example, high electron mobility and peak velocity of InP-based material systems have resulted in transistors with fmax above 1THz. The wide energy bandgap of GaN has enabled large voltage swings as well as high breakdown voltage RF power devices and the excellent thermal conductivity of SiC makes tens of kilowatt-level power switches possible [1]

[1] S. Raman, “The DARPA Diverse Accessible Heterogeneous Integration (DAHI) Program: Towards a Next-Generation Technology Platform for High-Performance Microsystems”, 2012 CS Mantech Conf.

DARPA proposes  that the future of CS electronics depends not on displacing Si, but rather on heterogeneous integration of compound semiconductors with silicon technology in a way that will take advantages of the two technologies when combined.

Past attempts at heterogeneous integration has been at the module level, i.e Multichip Modules [see “Multichip Module Technology Handbook” , P. Garrou, I Turlik Eds., McGraw Hill, 1998].

However, MCM techniques have been limited by I/O parasitic effects between chips in such modules and by device and interconnect variability issues. Many of the limitations including I/O parasitics and phase mismatch are governed by the length of separation between CS and Si CMOS devices, and as such, reduction of this separation is expected to yield dramatic improvements in performance of heterogeneous integrated circuits.

The COSMOS [ Compound Semiconductor Materials on Silicon] program began in 2007 with teams led by Northrup Grumman, Raytheon and HRL (Hughes Research Labs).  They have demonstrated three different approaches (see below) to achieving InP BiCMOS integrated circuit technology featuring InP HBTs and deep submicron Si CMOS for RF and mixed signal circuits.



The Northrop Grumman technology starts with a completely fabricated standard CMOS wafer. A separately fabricated InP HBT wafer (thinned to approximately 55u m) is mounted to a glass carrier. An InP wafer is etched to form individual chiplets (still attached to the carrier wafer). The CMOS wafer is prepared for integration with the InP chiplets by depositing gold (Au) micro bumps (3-10um and 2um thick). The glass carrier containing the singulated InP chiplets is then aligned to the CMOS wafer, and the bonding operation performed using standard wafer bonding equipment with controlled time, temperature, and bonding force. The glass carrier wafer is then released, leaving the singulated InP chiplets connected to the base CMOS wafer. This is shown schematically below.



DARPA is also pursuing the integration of GaN transistors with Si CMOS on a Si substrate.  For example. the Raytheon team has recently demonstrated a monolithically integrated RF amplifier circuit  using heterogeneously interconnected GaN HEMTs and pMOS gate bias control (see below).

Raytheon GaN


DAHI (Diverse Accessible Heterogeneous Integration)  initiated in 2013 is based on its predecessor COSMOS and is composed of several design, technology and manufacturing thrusts including :

  • Si CMOS for highly integrated analog and digital circuits
  • GaN for high-power/high-voltage swing and low-noise amplifiers
  • GaAs and InP HBT and HEMT for high speed/low-noise circuits
  • Compound semiconductor optoelectronic devices for direct-bandgap photonic sources and detectors, as well as or silicon-based structures for modulators, waveguides, etc.
  • MEMS components for sensors, actuators and RF resonators
  • Thermal management structures

Program teams include:

  • Teledyne/Tezzaron/UC Santa Barbara
  • MIT/Raytheon/Stanford
  • IBM/Columbia U/MIT/Veeco
  • NG/Novati/Nuvotronics/MOSIS/ON Semi
  • HRL/ UC San Diego/U Mass/U FLA
  • Raytheon/Novati/IBM
  • Rockwell/Tower Jazz/UCSD

At the recent DAHI program review in Boulder participants shared their technology progress to fabricate multilayer circuit structures (i.e InP, Si, GaN) on substrates such as SiC using 3DIC technologies such as TSV and oxide-oxide bonding.

The  goal of DAHI is to establish a manufacturable, accessible foundry technology for the monolithic heterogeneous co-integration of diverse (e.g., electronic, photonic, MEMS) devices, and complex silicon-enabled architectures, on a common substrate platform for defense and commercial users. By enabling the ability to ‘mix and match’ a wide variety of devices and materials on a common silicon substrate, circuit designers can select the best device for each function within their designs.  This integration would provide DoD systems with the benefits of a variety of devices and materials integrated in close proximity on a single chip, minimizing the performance limitations caused by physical separation among devices.

As these technologies become public, IFTLE will keep its readers apprised of the results.

For the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 205 2014 ECTC part 1: Controlling Warpage in Advanced Packaging

By Dr. Phil Garrou, Contributing Editor

We are a bit out of chronological sequence, but as usual the ECTC was chuck full of materials worthy of coverage. Since the presentation is in six parallel sessions it takes time to go back and read all of them, and, since the papers are published in IEEE Explore, I do not have the power point presentations to summarize for you.

Let’s start off with some papers concerned with warpage issues.

Hitachi Chemical

As we continue to miniaturize, warpage remains the main problem encountered in all areas of advanced packaging. Kotake of Hitachi Chemical addressed “Ultra low CTE core materials for next generation thin CSPs” They describe ultra low CTE (1.8) core materials (E-770G) which are used to reduce warpage in PoP packages. Hitachi simulations show that the CTE of core materials has more impact that the modulus.

Hitachi 1


Best results are obtained when using the new material E-770G for both core and prepreg.


Kim and co-workers at Amkor reported on “Strip grinding Introduction for thin PoP.” Typical PoP used in mobile products consists of a logic function In the bottom package and a memory function in the top package. The most difficult barrier to fabricate the thin PoP is warpage control. Amkor TMV (through mold via) PoP structures can be overmolded or exposed die (to allow for heat sinking). When trying to thin the package, there is a limit to the  thinness of the overmold and a limit to the silicon die thickness since thinner die result in die chipping or cracking during handling. In the thin mold cap case, it’s not easy to control the package warpage. The warpage can be controlled with a thicker substrate, but this increases the package thickness.

The concept of strip grinding is to grind the mold compound and die together. The advantage of strip grinding is to use normal die thickness and mold cap thickness, thus reducing the risk of thin die handling and narrow mold clearance. Mold flash is eliminated through the grinding methodology. By applying a strip grinding process, we can easily generate a very thin die and mold cap.

amkor 1


Double side molded structures are possible, which help make a balanced structure on top and bottom which tends to improve the warpage performance. Bottom side mold is difficult, because the BGA ball is mounted on the bottom area.

For the double-sided mold process flow, chip attach on the top side and BGA ball attach on the bottom side need to be done first followed by double side mold. The bottom molding is ground until the bottom ball is exposed. To remake a BGA, a second ball attach needs to be performed to generate a proper BGA standoff.

amkor 2


Warpage simulations were done for a variety of die/substrate/mold thicknesses, as shown below.

amkor 3


Warpage is minimized when (a) thin die is double-side molded, i.e leg 6; (b) very thin die i.e leg 3 or (c) thick substrate to balance mold, i.e leg 1.


Bchir of Qualcomm discussed “improvement of substrate and package warpage by copper plating optimization.”

While substrate warpage is typically approached through modification of dielectric material properties (such as CTE, Tg, modulus), layer thicknesses (core, prepreg, solder resist and Cu thickness), and Cu areal density per layer there is also an impact from the Cu plating process. Electroplated Cu thin films have porous grain boundaries, wherein grain boundary volume is strongly dependent on electroplating conditions and subsequent thermal processing.  During thermal processing, Cu grains grow and merge, eliminating grain boundaries and causing shrinkage. The residual stress in the initial deposit, coupled with shrinkage during subsequent thermal processing, strongly impacts the warpage of the substrate and package. This is compounded by the inherent front-to-back Cu density imbalance which is typical in substrate design.

Choice of electrolytic Cu plating solution has significant impact on the magnitude of package warpage. The influence of Cu plating solution on warpage is related to the resulting grain size distribution and stress state deposited from a given chemistry. Plating additives can be co-deposited as impurities into the Cu layer, and have been shown to strongly impact residual stress and grain coarsening behavior of the Cu deposit.

They found that reducing the plating current density for a given plating solution led to substantial reduction in package warpage. Also,  an increase in the plating current density causes a reduction in the deposited grain size, hence a reduction in current density would lead to larger deposited grains and thus larger grains would mean reduced grain boundary volume, less “shrink” in the Cu layer and lower residual stress in the Cu.


Eric Beyne’s group at IMEC detailed their work on “Minimizing Interposer Warpage by Process Control and Design Optimization.” Imec’s silicon interposer technology consists of 10×100μm TSV, four thick damascene BEOL layers, Cu bumps and redistribution layers (RDL) front side and back side.



They calculated and measured 300mm wafer bowing at different stages of interposer BEOL processing, as shown below. There is good agreement between simulation and measurement. For a 10mm x 20mm interposer, bowing is measured as 30um (short side) x 130um.



Bowing mitagation was investigated by:

-  Replacing standard Pre-Metal-Dielectric (PMD) layer by a thicker and more compressive insulator

- The use of thinner Metal1 and Metal2

- The use of a more compressive oxide in the BEOL

- Replacing the standard PMD layer (300 nm/80 nm SiO/SiC layer) by a thick PECVD oxide with -170 MPa compressive results in a bow reduction of around 150 um (-37% bowing).

At die level,  bowing value of around 45 μm (-59% bowing) is predicted by the model for a 20 x 20mm  interposer.



The use of thinner Metal1 and Metal2 will increase the sheet resistance of the two layers and consequently may impact the electrical performances of the interposer. The figure below shows that reducing the thickness of M1 and M2 effectively reduce the bowing and that a thickness of around 0.4μm could be a good trade-off between bowing and performance decreases.



Small modification of the stress of the oxide can be very efficient to decrease the bowing at wafer but also thin die level.



They conclude that “the use of a more compressive and thicker PMD insulator layer, a reduction in Metal1/Metal2 thickness, the use of more compressive oxide within the BEOL, are promising and easy to implement solutions to reduce interposer bowing with a limited impact onto its performances.”

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 204 IBM / GF Semi Deal: the drama continues; Leti Studies Monolithic 3D

By Phil Garrou, Contributing Editor

Reports a week ago indicated that “It appears that IBM’s sale of its microchip manufacturing business to GlobalFoundries had fallen apart.” [link]

The local paper, the Poughkeepsie Journal, citing “anonymous sources with knowledge of the inner workings of IBM”, said the deal had been known under the codename  “Project Next.” Reportedly IBM managers at East Fishkill were told July 15th that the deal to sell its microchip unit to GlobalFoundries was off. The Journal quoted consultants who felt that such a deal would likely need clearance from federal agencies since IBM is a so-called “trusted foundry” for the U.S. military and GlobalFoundries is owned by the government of Abu Dhabi [link].

Perhaps, but…

 Bloomberg reported on Aug 5th that “according to a person familiar with the process”, it was  IBM offering to pay GlobalFoundries to take on IBM’s money-losing chip-manufacturing operations [link].

According to Bloomberg contacts, IBM was offering about $1 billion to entice Globalfoundries to take the unit but  Globalfoundries wanted $2 billion. Recall it has been reported that the IBM Semi business has been losing ~ $1.5B / year for several years.

It is likely that IBM requested GF continue operation of the two facilities to maintain supply of chips that they are using in IBM products. To do so GF would likely continue to incur similar losses and that may have outweighed acquisition of whatever IBM IP was to be included in the deal. IFTLE’s  understanding is that Burlington could be made to operate as an analog / specialty division, but East Fishkill (which reportedly cost $2.5B to build) should just be closed down because it is old and outdated.

With IBM semiconductor employees understanding that their division is no longer wanted by IBM corporate, many are jumping to GlobalFoundries which is actually setting up “job fairs” in the IBM factory communities [link].

It appears to IFTLE that IBM does not have much leverage in all of this, but we will see as the drama continues.

Leti Continues to Study Monolithic 3D

In Dec 2013 Qualcomm, in a move that appeared to show impatience with the development of 2.5/3DIC infrasructure, announced an agreement with CEA-Leti, to assess the feasibility and the value of Leti’s sequential (monolithic) 3D technology. In comparison with 3D-TSV technologies which  stack separate die, sequential 3D technology proposes to process all the functions in a single semiconductor manufacturing flow. Thus, the technology allows connecting active areas at the transistor level, at a very high density as it uses a standard lithography process to align them.

According to Leti, this technology is expected to produce a 50% gain in area and a 30 percent gain in speed compared to the same technology node in 2D. They expect the  sequential 3D technology will be much less complex and expensive to implement than sub 22nm nodes , making this technology a potential alternative to conventional planar scaling.
At the recent Semicon West event in San Francisco, Olivier Faynot, devices department director at CEA-Leti updated the community on their results thus far. According to Faynot the design kit is ready since technology is standard CMOS processing.

Leti 1
As expected, the issues are all thermal due to the sequential processing.

leti 2

It is hoped that advanced laser processing will allow proper dopant activation without disturbing lower layers.

Leti 3


They report that initial results show thermal stability demonstrated up to 500°C at 28nm and 14nm SOI nodes.

Key points ae reportedly silicide stability and dopant deactivation for NMOS.  On going process work includes:

• W implantation    • NiPt deposition    • Silicide formation    • F implantation

• RTP at various durations and T°

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 203 Apple Acquires LuxVue µ-assembly Technology

By Dr. Phil Garrou, Contributing Editor

Apple has acquired 24 tech companies in the last 18 months. Recently, Apple acquired LuxVue, a start-up focused on low power micro-LED displays. Although Apple has not disclosed any details of the acquisition, not even the purchase price, one can easily envision where micro LED displays could play a big part in Apples thrust into wearable electronics such as the i-watch. Reportedly the LuxVue display is 9 times brighter than both LED and LCD screens.  Such µ LED displays would be compatible with curved surfaces and would save power and thus increase battery life. Brighter, lower power displays could have applications in other Apple products and products such as Google glasses.

Little is known about the LuxVue technology other than the patents that have been issued. They have no web page and have made no public presentations that I can find. The do have several dozen patents many of which deal with transferring micro devices, which specifically for displays would be LED devices as small as 10 x 10 miron and placing them on 10 micron pitch.

Their preferred transfer device consists of a substrate with an arrangement of protruding mesas. Each mesa contains electrodes with a thin coating of dielectric. By providing a charge between the electrodes, an electrical field is created which electrostatically attracts the miniature chips or LEDs [for example, see USP 8333860 B1].

It is proposed that using this approach one can selectively choose to remove specific micro devices from a source substrate by applying voltage only to the projecting mesas corresponding to the positions of the device to be transferred.

In essence, this is massively parallel pick and place. We are all familiar with conventional pick-and-place assembly using vacuum collets and pin ejectors. For devices that are on the scale of 10 micron however, manipulation and accurate placement are significantly more difficult with today’s tools. This LuxVue “electrostatic chuck” mechanism is one way to deal with manipulation of such small devices.

If massively parallel pick-and-place sounds familiar, recall similar technology Semprius and more recently X-Celeprint have been developing.  These startups are based on the work of John Rogers at U. Ill. Which uses PDMS stamps rather than the more complex electrostatic chuck. [link 1] [link 2]

I have compared the two technologies in the figure below:

Xceleprint vs luxvue


I contacted Professor Rogers and X-Celeprint CTO Chris Bower, and they agreed that microassembly of such LEDs is indeed the sweet spot for X-Celeprint technology. They sent the images below which show some early examples of transparent and flexible devices using Micro-Transfer-Printed inorganic LEDs. At this point, they were just willing to say that this was an area “of active interest.”

Double printing the RGB LEDs allows circuit redundancy, so a bad LED or connection does not produce a bad pixel. This is the technique already in use by display manufacturers [link 1] and more recently 3DIC practitioners to insure that a bad TSV does not result in a failed chip [link 2].


As devices continue to get smaller, we can expect to see micro transfer technologies such as these take a more prominent role in their assembly.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 202 ConFab 2014: Novati, Lumileds; Chipworks; IEEE CPMT Packaging Panel

By Dr. Phil Garrou, Contributing Editor

Dave Anderson, CEO of Novati talked about “More-than-Moore, Advanced Packaging and Creating Game-Changing Innovation.” In keeping with the main theme expressed by IFTLE for several years, Anderson echoed, “Most companies can’t afford to continue to pursue Moore’s Law scaling” and offered “More-than-Moore” as a product customization route for the future.

Andrew Kim of Philips Lumileds updated attendees in “Trends in LED Manufacturing.” (As you may recall IFTLE and its incarcerated spokesman Lester Lightbulb are not strong supporter of LED replacement  of the incandescent bulb, i.e. see IFTLE Lester Lightbulb.)

Kim presented a “very simplified” process sequence for LEDs manufacturing. (“Wow that sure should be cheaper and better for the environment than a tungsten filament bulb.” – Lester) In addition, as we have shown before, the new light sources are not only the “electroluminescent emitter,” but a far more complicated circuit of PCB and components [see IFTLE 63 “Bidding Adieu to Lester the light bulb”]

Limileds 1


Kim sees the following options developing for substrate alternatives.

– Sapphire: currently dominant, current substrate cost for larger sizes

– Silicon: Manufacturing and performance

– GaN on GaN: Cost and value proposition

– SiC: Single LED user with captive source

Evidently the DOE game plan is still to reach $8 / bulb by the early 2020’s. (“Wow that will make it only 16X the cost of an incandescent bulb” – Lester)

lumileds 2


LEDs certainly offer new form factors for light and in the future will allow creation of devices that we are not today thinking about.  IFTLEs issue with LED lighting is with how it was sold to the consumer as a saver of power and a saver of cost. IFTLE arguments have been presented previously and can be found here [link].

By the way, we are now more than three years into our single bulb testing which was started in Aug 2011. The CFL was dead in < 10 months but the LED and the incandescent are still burning bright 3 years into the testing. Remember the incandescent cost me only 50 cents.

Fellow SST Blogger Dick James from Chipworks shared “Inside Today’s Systems & Chips: A Survey of the Past Year”. During their reverse engineering of the Apple iPhone 5s, Chipworks identified the CMOS image sensor as Sony’s  AW34 5399.

chipworks 1


IEEE CPMT Packaging Session


Bill Chen of ASE put together an Advanced Packaging panel to update ConFab attendees on the latest packaging advances.

packaging group


Garrou (IFTLE), Chen (ASE), Huemoeller (Amkor), Bezuk (Qualcomm) and Black (AMD)

The presentations of Amkor, Qualcomm and AMD have been reviewed recently by IFTLE [ see: “IFTLE 179 GaTech Interposer Conf: Amkor, GlobalFoundries”; “IFTLE 186 IMAPS Device Pkging Conf: Qualcomm, Prismark”; “IFTLE 188 IMAPS Device Packaging Conf Part 2: AMD, SCP”.

As part of my presentation, I looked at the status of a few of the 3DIC rumors that we have discussed on IFTLE, which didn’t come true and the current status of announced products including Hynix stacked memory, Microns HMC stacked memory and graphics modules from Nvidia. Memory is now happening, so hopefully the rest of the products will be coming soon.

Garrou 1


For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 201 2014 ConFab: Global Foundries; IBM, G450C

By Dr. Phil Garrou, Contributing Editor

Yes, we have now passed numero 200 on what I shall self proclaim the #1 informational blog for 3DIC and advanced packaging on the internet! Again, my thanks to Pete Singer for continued support.


Now that you have taken a look at us, let’s take a look at some of the presentations at this year’s ConFab.  Subramani Kengeri, Vice President, Advanced Technology Architecture for GlobalFoundries discussed the techno-economics of the semiconductor industry.

Emerging applications will include:


1. Computer vision

2. Augmented reality

3. Concurrent application and modem operation

4. Gesture recognition

5. Medical applications

6. Contextual awareness

7. HD video and games

8. 3D camera and 3D display

9. Multiple concurrent displays

10. Multiple concurrent audio and video CODECS

Kengeri concludes that “the semiconductor industry is challenged on the Economics of technology scaling.” Cost of building a new leading edge fab continues to escalate while capex / wafer is increasing at a rate of 38%.

Click to enlarge.

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In addition, ROI is delayed due to increased investment requirements and longer time to volume.

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GF also offered some interesting insights into the industry landscape.

Click to enlarge.

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Gary Patton, VP of IBM Semiconductor Research & Development Center addressed “Semiconductor Technology: Trends, Challenges, & Opportunities.” Patton confirmed that scaling beyond 22nm will require alternative device structures and new material innovations.


Click to enlarge.

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Beyond silicon, packaging and board innovations are required to continue to miniaturize. IBM points to interposers and die stacking to do this.


Click to enlarge.

Click to enlarge.

Adrian Maynes, 450C program manager, discussed the “450mm Transition Toward Sustainability: Facility & Infrastructure Requirements.”

G450C is a public/private program based at the College of Nanoscale Science & Engineering in Albany with goals of :

-  Driving effective industry 450mm development

-  Focus on process & equipment development

Members include Intel and the major foundry players and for now IBM (rumors of their acquisition by GF remain rampant).

G450 1

The consortium sees the following changes coming between 300mm and 450mm.

G450 2

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…


IFTLE 200 Semicon West Suss Workshop: Laser Debonding and KLA Tencor platform for WLP inspection

By Dr. Phil Garrou, Contributing Editor

The 5th annual Suss Technology Forum was recently held at SEMICON West focused on trends in 3DIC and WLP.

Stephan Luetter compared the various temp bonding technologies and their current focus on excimer laser assisted release.   The EDL-300 is their eximer laser debond module which rasters the wafer with a 12x 4mm laser beam. Carrier is lifted of with a vacuum gripper with close to zero mechanical lift-off force. A requirement for laser assisted debonding, is that it uses a glass carrier wafer to allow transmission of the laser light. Suss has concluded that the new materials and simpler process flows allow cost of equipment reduction in the range of 1.5-3X.

Suss temp 1


The Suss open platform program supports 10 materials suppliers and 4 laser assisted RT debonding processes (including 3M, Brewer, Dow and HD Micro).

suss temp 2


Kim Arnold of Brewer introduced their 3rd generation temporary bonding solution BrewerBond which makes use of a laser assisted room temperature debond process.  Brewer who has been supporting the 3DIC infrastructure for a decade has introduced several product families to meet their customer needs. Each generation has increased throughput and thermal stability better allowing backside processing at higher temperatures.

brewer 1


The BrewerBond process makes use of a light sensitive layer which is decomposed during debonding with a 308nm excimer laser. Arnold indicated that development of a gen 4 product with higher throughput and higher thermal stability is underway.

Mark Oliver of Dow Chemical discussed their laser bond release process. Laser debonding at 308nm is shown below. The adhesive ends up on the device wafer side and is removed with a simple tape peel.

dow 1


Dow also proposed the use of temp bonding to deal with warping in technologies such as fan out WLP.

dow 2


Sood of KLA Tencor announced their CIRCL (Concurrent Inspection and Review Cluster)  platform to address inspection requirements for advanced WLP.

KLA Tencor 1


For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 199 Omnivision Roadmaps 3D stacking for CMOS Image Sensors; IC Insights Details Trends Shaping the IC Industry

By Dr. Phil Garrou, Contributing Editor


Since Toshiba started using backside TSV in 2008 we have been anticipating  stacking of separate functions in true 3DIC fashion. Last summer, Sony announced such a structure.  [link 1]

Recently, at the  image sensors conference in London, Dr. Howard Rhodes, CTO of Omnivision, gave an keynote entitled “The Future of CMOS Imaging” where he expounded on the advantages of stacking and the separation of the imaging function from the logic function.

fig 1



Of special interest are Rhodes comments on “stacked CIS” which he calls “replacing the BSI Si substrate with logic.” Their roadmap shows Omnivision moving from wafer bonding with simple oxide bonding to “hybrid bond stacking with simultaneous bonding of oxide and Cu contacts to 3 wafer stacking where sensors, ISP and memory are fabricated separately and stacked.

fig 2


Longtime readers of IFTLE will recognize that Gen 1 “Oxide-oxide” bonding is the technology Sony licensed from Ziptronix in 2011 [link].

“Hybrid bonding” is the term commonly used to describe the patented Ziptronix DBI process where oxide and copper (or other metal) bonding occurs simultaneously [link], so one should expect to see more Ziptronix licensing in the future.

IFTLE would guess that there will be further licensing in Ziptronix future.

IC Insights

At the recent SST ConFab in Las Vegas Bill McClean shared his annual report on  “Major trends shaping the future IC Industry.” IC insights reports that recent growth in the IC industry has been mainly in memory.

fig 3


For the first time in 2013, communication surpassed computers in terms of market share.

Fabless sales are now 29% of total IC sales with the US is holding its ~70% market share of fabless market sales which it has had since 2010.

fig 4


The bulk of capex spending is being done by the major players, i.e. the ones who appear set to move forward to lower nodes (1-7 in the chart below).

fig 5


Over the last two decades, the percentage of capex being spent by the top 5 has steadily increased to its current 70% with the big three of Samsung, Intel and TSMC being responsible for over 50%.

fig 6


A look at capital spending by region shows Japan and Europe falling for behind with a combined sub 10%.

fig 7


r all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 198 Intel & Micron HMC 3D Stacked memory; GS Nanotech announces 3DIC Plans; STATSChipPAC suitors named

We have all been waiting a long time to see the following headline:

Intel to Commercialize HMC  Stacked Memory – Knights Landing

Last week at the 2014 ISC (International Supercomputing Conference) it was announced that the Intel Xenon Phi processor “Knights Landing” would debut in 2015. [link] It will be manufactured by Intel using 14nm FinFET process technology and will include up to 72 processor cores that can work on up to four threads per core. It will support for up to 384 GB of on board DDR4 RAM  and 16GB of Micron HMC stacked DRAM on-package, providing up to 500GB/sec of memory bandwidth. It will be the first Intel processor to use this new high performance on package memory.

Intel 1

The Micron 3D stacked  memory which we have know as the hybrid memory cube for several years is being called “multichannel memory or MCDRAM. Micron reports that having such memory in the CPU package is expected to deliver 5X the sustained memory bandwidth versus GDDR5 with one-third the energy per bit in half the footprint.

micron 4

Knights Landing is expected to be deployed in various high performance computing solutions such a as the Cray “Cori” at  National Energy Research Scientific Computing (NERSC) Center.

Long time IFTLE readers recall that Intel was involved from the beginning with the concept of HMC [ see IFTLE 74, “The Memory Cube Consortium” ] and in fact shared a glimpse of the memory cube technology at their developers forum in June of 2011.[link]

fig 5 IDF 2011

Recall Micron contracted IBM to manufacture the logic interface layer [see  IFTLE 95, “3DIC – Time Flies When You’re Having Fun; Further Details on the Micron HMC….”]

So it was interesting to see the logic layer on display recently in the IBM booth at ECTC. I’m pretty sure this is it (before the memory layers are attached).

IBM logic layer 2

While the excitement level around this announcement will be high, we should all understand that as described this is a high end HPC application, not the high volume driver that the 3DIC world has been awaiting. The question for intel is will Intel use this as a platform to compete with nVidia and AMD/ATI on graphics, or will this be just a niche HPC product?

We should also note that although Intel has numerous patents in the area, there is no current indication that this will be a 2.5D solution. Intel has thus far only said “it will be high bandwidth.”

GS Nanotech

Anyone else surprised by the recent announcement that GS Nanotech (Kaliningrad, Russia) “plans to launch mass assembly of 3D stacked TSV microcircuits in the next few years”? I must admit I had never heard of them. A quick look at their web page indicates that they manufacture chips for General satellite set-top-boxes and have ST Micro, Nanium, Toshiba and Winbond listed as customers.

FYI – we are in the process of inviting them to speak at the RTI ASIP conference in December to see exactly what they have and what their plans are.

Updating STATSChipPAC

From our friends at Digitimes: “STATS ChipPAC, the world’s fourth-largest IC backend service company, has put itself up for sale with ASE, Changjiang Electronics Technology, Samsung and Huatian Technology (Xian) likely to compete for the sale… STATS ChipPAC has been holding talks with potential buyers since mid-May, with ASE and Changjiang being the first two contenders… Changjiang aims to enhance its manufacturing technology and patent portfolio, and to ramp up total capacity by acquiring STATS ChipPAC, noted the sources… ASE’s bid for STATS ChipPac is more likely to prevent other potential competitors from taking over STATS ChipPAC to build up capacity against ASE…” Samsung, Huatian, Foxconn, UTAC and GlobalFoundries have also been rumored to be potential acquirers. [link]

For all the latest on 3DIC and other advanced packaging solutions, stay linked to IFTLE…

IFTLE 197 IBM / GF; 3D Integration Handbook Volume 3; 2014 iTherm

IBM/GF …the Saga Continues

Although both IBM and GF are refusing to address “rumors and speculation,” the rumors and speculation persist that the sale of IBMs semiconductor business to GlobalFoundries is imminent. The latest to comment on the expected deal is Businessweek / Bloomberg [link]

Most experts feel that GlobalFoundries is primarily interested in acquiring IBM’s engineers and intellectual property rather than the manufacturing facilities (200mm facility in Burlington VT and 300mm line in East Fishkill NY) since GF has its own state of the at capacity. GF would  act as a supplier for IBM’s semiconductor needs.

Reading the Vermont Free Press articles on the subject, it is clear that IBM employees expect GF to mothball the facility. For those of you wondering why there is a semiconductor facility in VT at all I offer you the following interesting comment “IBM opened its plant in Essex Junction in 1957, largely because the late Thomas Watson Jr., former IBM chairman and CEO, liked to ski.”

3D Integration Handbook

bookMitsumasa Koyanagi, Peter Ramm and I have finished our work on Volume 3 of the 3D Integration Handbook and it is now available for sale at Wiley VCH, Amazon or you favorite textbook retailer.

Vol 3 focuses on 3D Process technology, updating the original two volumes in 2008 with all new chapters on all the relevant process steps. We have gathered many of the worlds experts to give you their insights on 2.5 / 3DIC processing and an especially strong chapter on metrology from the staff at Sematech. The bond/debond section includes chapters by Brewer, EVG, Suss, TOK , 3M and RTI. Most areas are covered by at least two different authors to give the reader a more complete perspective of what is possible. Of special interest should be the chapters “Bonding and Assembly at TSMC” by Doug Yu, “Cu TSV Stress: Avoiding Cu Protrusion and Impact on Devices” and “Implications of Stress/Strain and Metal Contamination on Thinned Die” by Kangwook Lee.

Paul Franzon of NC State, Eric Jan Marinissen and Muhannad Bakir will be editing Volume 4 which will focus on Design, Test and Thermal. We hope these volumes prove to be of value to the community.

2014 iTherm

iTherm is the Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems. The 2014 iTherm was held concurrent with the ECTC in Orlando, FL. This years General Chair was Mehdi Basheghi of Stanford and program chair was Madhusudan of Google. Attendance this year was up 50% to ~ 400.


Kumari and co-workers at HP addressed “Air Cooling Limits of 3D Stacked Logic Processor and Memory Dies.” Their goal was to determine how many memory die can be integrated into a package with logic before exceeding the temp limitations of the memory die. Modeling was done for 10nm technology with 24 cores as shown below. Core power is varied from 1.5 to 3 W (red cores). Sacked memory are 0.5W DRAM.

HP 1

Thermal results are shown below.

HP 2


Oprins and Beyne discussed the “Thermal Modeling of the Impact of 3D Interposer Materials and Thickness on Thermal Performance and Die-to-die Thermal Coupling.” For the test vehicle shown, they observe reducing the thermal conductivity from Si to glass results in an increase in the logic temperature and consequently a lower maximum logic power. The memory temperature at the other hand decreases for decreasing values of the conductivity since the in plane thermal coupling is reduced. This results in an increase of the allowable logic temperature. If the memory heating is included, an increase of the memory temperature can be observed for very low conductivity values.


Most applications for interposers combine high power components (logic) and temperature sensitive components (memory). Since the components are thermally coupled in the package, the logic power will be limited by either the temperature limit of the logic or memory, whichever is reached first. This means there is a trade-off between the logic self-heating and the thermal coupling which are impacted differently by the interposer material and thickness choice. It is shown that the Si interposer has a better thermal performance than the glass interposer in case only the logic temperature limit is taken into account and that the Si interposer package thermally outperforms the single chip package, the package-on-package configuration (PoP) and the 3D stacked configuration. In case the memory temperature limit and self-heating are taken into account as well, the glass interposer package has a better thermal performance for cases where the memory temperature limit memory is sufficiently lower than logic temperature limit.

For all the latest in 3DIC integration and other advanced packaging, stay linked to IFTLE…