NC State – TSV Test prior to stack
During wafer test, it is valuable to be able to determine which TSVs are likely to yield when used, and which are not. To detect failure in TSVs, an electrical test needs to be performed before 3D integration and chip packaging. Paul Franzon and co-workers at NC State propose three methods to test Through-Silicon-Vias (TSV) electrically prior to 3D integration: (1) sense amplification; (2) leakage current monitor; and (3) capacitance bridge methods. These tests detect one or both of two failure types, pin-holes and voids. The test circuits measure capacitance and leakage current of the TSVs, and generate 1 bit pass/fail signal. All these methods can be implemented for test-before-stacking, to attempt to increase assembled yield.
The sense amplification and the capacitive bridge test structures can estimate the TSV capacitance to test void defects. The capacitive bridge circuit is more sensitive but consumes more area than the sense amplifier sensor. The sense amplification method cannot detect voids isolating less than approximately ±10% of the TSV. The potential test escape rate is proportional to what percentage of TSVs that have voids isolating 10% of the TSV capacitance or less. The leakage current test circuit can measure the resistance of dielectric layer to test leakage defects with much more sensitivity than the sense amplifier method. All the simulation results above show that the parameters of TSVs can be tested by simple circuits and the measurement data can be streamed out serially by a scan chain.
TSMC – Electrical Tests for 3D IC with TSV
Chen and co-workers at TSMC have identified five main categories of “faults” (i.e. performance failure modes) in 3DIC TSV with microbumps:
1. Faults due to miss-alignment
2. Faults in the Cu pillar
3. Faults due to impurities
4. Faults due to substrate
5. Faults in the microbump
In terms of alignment, they report two possible failure issues. The type 1 failure is due to an alignment shift which results in smaller overlap area contact and thus higher resistance. The type 2 failure occurs when there is severe miss alignment and a complete open occurs.
The second category is related to the Cu TSV. Type 3 failures come from voids in the Cu TSV which may be caused by electromigration. The resistance in the TSV becomes larger and the RC delay increases. Type 4 failure occurs due to breakage in the TSV by improper handling or other procesing issues and will result in an open circuit. The type 5 failure is due to failure to completely fill the TSV. This will also increase delay due to the higher resistance.
The third failure mode is due to impurities during processing. Type 6 failure is due to impurities between the TSV and the microbump which increase the contact resistenace and thus the signal delay time. Type 7 failure is due to impurities between the microbumps which also increases the contact resistance and thus the signal delay.
The fourth and fifth failure modes deal with failures in the substrate and failures in the microbump. Type 8 failure is due to non uniformity in the insulation liner which can result in a leakage path from the TSV to the substrate. Type 9 failure results in an open circuit from Cu TSV delamination from the substrate due to the thermal stress of the process. Type 10 failure is due to deformation of the microbumps or the wafer warping and the separation of the two microbumps causing discontinuity. Type 11 failure is due to shorts between the two microbumps.
The Table below compiles failure modes vs required testing which includes continuity, resistance, capacitance, leakage and high frequency performance
In a presentation covering DFT (design for test) Qualcomms Michael Laisne concludes that there are two primary defect classes: a) interconnect related defects and b) stress related defects. Either of which could manifest itself as a “stuck-at” or speed-related failure. He lists the main causes of interconnect-related defects as:
– substrate to TSV shorts,
– parasitic capacitance or resistance between the substrate and TSV causing speed-related failure,
– capacitive coupling between adjacent TSV causing both static and at-speed failures
– microbump opens and shorts, especially due to excessive warpage (opens) and misalignment (shorts)
– shorts due to interactions with TSV’s
– shorts and opens in the RDL
Stephane Lecomte of ST Ericsson reports that the first 3D TSV application they foresee in cell phones is wide IO memory which is currently undergoing JEDEC standardization. We have recently reported on similar conclusions from Nokia [see IFTLE 19,”Semicon Taiwan 3D Forum Part 2” ]
Most of the manufacturing issues, they feel are still tied up in the business model / infrastructure / supply chain issues that have yet to be resolved. They feel that boundary scan testing will be defined within JEDEC, but that BIST remains very manufacturer dependent.
ARM presented an interesting slide depicting the Mb/sec requirements for several common devices (shown below)
Certainly we would all agree that 3D IC test has come a long way over the last few years. All of the major design and test companies are now focused on integrating products so that full 3D IC integration can become a reality in the near future. For those worried that 3D still looks like it is many years away, I refer you back to the Qualcomm presentations that indicate that first generation products do not appear to have significant roadblocks in either thermal, design or test. It is for the future generation partially or fully reconfigured structures that major changes in design and test will be needed [ see IFTLE 9, “3D in and Around the Moscone”
Lastlyâ??¦..One of the IEEE 3D Test Conference chairs requested that IFTLE model their midnight black knit shirt, so below we find our “mature” model showing off his shirt while reading the New York Times # 1 non fiction best seller “Handbook of 3D Integration” by Garrou, Bower and Ramm, available at Amazon.com !
For all the latest in 3D IC and advanced packaging in 2011 and beyond, stay linked to IFTLEâ??¦â??¦..