Insights From Leading Edge

IFTLE 7 Stacking Chips in Vegas

…Finishing our look at 3D IC papers at the 2010 ECTC in Las Vegas.


Various approaches have been studied and reported to debond the thinned wafer from the mechanical carrier wafer including thermal release, chemical dissolution and laser ablation. The laser ablation method utilizes a glass handle wafer and can be performed at room temperature for a wide range of polymeric adhesives that have proper bonding and absorption characteristics. Using controlled laser ablation parameters, IBM  reports that a 200mm wafer can be debonded after a single ablation pass for less than 1.5 minutes.


The TOK Zero Newton temporary bonding process has been discussed previously [ see PFTLE 77, Temporary Bonding for 3D Thinning and Backside Processing, May 25 2009] .

IBM and TOK have now examined the use of TOK temporary adhesives with 280 â??¦C thermal stability in the TOK Zero Newton wafer handling system. They find that both a high Tg and a high softening point are necessary for thermoplastic temporary adhesives. Materials with low softening point reportedly result in as high as 13 µm “rippling” (localized wafer bow) between the die which makes backside processing “..difficult to impossible”. The new adhesive shows a Tg of 168 â??¦C and a softening point of 270 â??¦C which results in stability at 280 â??¦C for > 1 hr and measured rippling of ~ 0.48 µm.

Temperature stability of 280 â??¦C is reportedly required to sustain exposure to backside processing such as PECVD, PVD and solder reflow. It is well known that the quality of plasma deposited SiO2 degrades as processing temperatures are reduced. No off-gassing is seen from this material below 300 â??¦C.

The TOK system is debond by a solvent dissolution process through a perforated carrier wafer, i.e. the thinned wafer is mounted on a film frame with the carrier perforations facing upwards, the debonding tool head is aligned with the handler and solvent is injected through the perforated carrier to gently dissolve the adhesive. Once the carrier wafer is removed, the thinned wafer on film frame is rinsed with solvent, washed and spun dry. Disolution rate is reported to be ~ 80 nm/sec.

Full 3D TSV process integration ( the full IBM process sequence for W TSV as IBM previously described in the 2006 ECTC) was carried out to show process efficacy.

CE Leti & ST Micro

Leti and ST Micro have studied the TEOS oxide deposition process in order to control parasitic capacitance for high frequency (1GHz) applications.

TEOS based SiO2 is deposited by PECVD. The deposition temperature is 260°C due to the thermal instability of the adhesive layer between the temporary carrier and the bonded membrane for temperatures above 250-300°C. The target specifications were a dielectric constant of 4.5, a leakage current below 5 x10-8 A/cm2 at 2MV/cm and a conformality sufficient to ensure the continuity of the insulation layer at the bottom of the TSV.

O2/TEOS ratios between 0.5 and 8 were examined . The density of the deposits were (surprising to IFTLE ) all identical. The effect of gas ratio on dielectric constant and leakage current are shown below.

The impact of gas ratio on permittivity is significant. As seen in the figure below the mean value of the Dk for the SiO2 deposit strongly decreases with the gases ratio, from 10.81 for a ratio of 0.5 to 4.56 for a ratio of 8. This is associated to the reduction of –SiOH, -SiH and –OH groups in the deposit film as evidenced by FTIR analysis. Only the O2/TEOS ratio of 8 results in an acceptable leakage current of 5.1 x10-8 A/cm2.

The form factor for memory in mobile devices is limited, therefore there is strong demand for stacked die packaging use TSV to achieve improved performance, increased operating speed and minimum volume. Eliida, Oki and NEC have previously described a stacked DRAM using poly Si TSV [PFTLE 87 NEC points to Ni for Memory 3D TSV, 07/19/2009] but their high resistance interface to the back contact has limited commercialization. We have also reported that in response to these performance issues, NEC has developed electroless Ni v/ immersion Au (ENIG) process for TSV [PFTLE refs] In this ECTC publication NEC details their vias last (backside ) TSV process.

Ni was selected as the plating material because it has a high plating rate (10 to 20 µm/h) and forms a barrier against Sn-Ag solder. W was chosen as the pad metal. Thermal annealing was required to obtain sufficient adhesion to both Si and W interfaces. TSV X-sect are shown in the fig below. Layers are stacked with Cu/(SnAg) bumps. Ni bump height uniformity was an issue that had to be closely monitored. Ni TSV were 0.14 Ω vs previous results for poly silicon which were 4.1 Ω.

Stacked DRAM are shown in the fig below. No indication of commercialization was given.

Fraunhoffer IZM / NEC Schott / Schott Elect Pkging

Michael Toepper and the IZM Berlin group working with Electronic Packaging & Schott GmbH have examined the feasibility of glass interposers. They have focused on W plugs sealed into glass wafers. Rerouting metal is electroplated Au or Cu on a adhesion layer of TiWAu. Bump UBM is deposited TiW/Cu/Ni/Au. Solder balls are attached by ball drop. The higher thermal resistance of glass vs Si means thermal issues will have to be carefully watched.

For all the latest on 3D IC integration and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦â??¦..


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.