Insights From Leading Edge



IFTLE 13 3D In and Around the Moscone Part 3

â??¦â??¦â??¦.Finishing our look at the 3D related events at the recent Semicon West exhibition.



EVG


Markus Wimplinger , Corp Tech and IP Director, shared that 3D and TSV have been a main focus for EVG during the downturn and they feel these technologies have served them very well financially.


Wimplinger sees the only 300 mm 3D line in production is the ST Micro CIS (CMOS Image Sensor) line. Line qualification is underway right now for several customers who should be finished by 4Q 2010. He predicts that some but not all of their customers will be ready for production in the 2011-2012 timeframe and that most of them will be in Asia. Those that are furthest along actually have process ground rules out to selected key customers but have not widely distributed them yet. He also notes that W2W bonding is on the upswing again after bottoming out (vs D2W) around 12 months ago.


Verigy


Mark Allison, VP of strategic Marketing indicated that Verigy is a member of both the IME (Singapore) and ITRI (Taiwan) 3D consortia. Allison reported that some of their customer base were exerting pressure for 3D IC test solutions while others appeared to be waiting to see further clarity in the infrastructure.


Some of the TSV test challenges that they have found include:


- TSV size vs probe capabilities


- making sure the DFT (design for test) probe pads don’t add capacitance and inductance to the TSV


- handling the complex functionality of the stack


Verigy is looking into putting DFT structures on interposer which is lower cost real estate.


Equipment Heavyweights Have a Change of Heart


In the past few years PFTLE and IFTLE have documented the move of Equipment heavyweights Applied Materials and Novellus into the here-to-fore shunned area of packaging. [See PFTLE 72 “Samsung 3-D ‘Roadmap’ That Isn’t”, 4/16/2009; IFTLE “...on Finding the Beef and Finally Addressing 3D IC”, June 2010]


It wasn’t so long ago that such heavyweights snubbed their nose at the packaging market. Well, the upcoming end to scaling and Moore’s Law (as we know it) sure have turned things around [ see PFTLE “IC Consolidation, Node Scaling and 3D IC”, 03/03/2010]. Topics like 3D TSV and WLP are now the darlings of the equipment industry.


Don’t get me wrong, having the big boys set their sights on packaging and 3D with TSV is positive and developments that they come up with can only improve things for all of us in the long run. With reports that 300 mm 3D lines are going intro place around the world “as we speak” it was to be expected that both would be in “full court press” mode at Semicon – and they were.


AMAT


Dr. Randhir Thakur, executive vice president and general manager of Applied’s Silicon Systems Group announced that Applied could now offer customers “…a complete toolset for all TSV manufacturing flows encompassing etch, CVD, PVD, ECD, wafer cleaning and CMP,” said. , Applied’s Maydan Technology Center and their activity at institutes like IMEC and ITRI can only help customers develop “.. a smooth transition from R and D to volume production” as they put it.


Novellus


Novellus introduced new models of the company’s VECTOR PECVD, INOVA PVD, and GxT photoresist strip systems specifically designed for WLp and 3D.


The newly-introduced SABRE 3D system addresses void-free filling, reduced copper overburden, and improved fill uniformity at higher throughputs. SABRE 3D’s modular architecture can be configured with multiple plating and pre-or-post-treatment cells for a variety of packaging applications including TSV, pillar, RDL, under-bump metallization, and eutectic and lead-free micro-bumping using materials such as copper, tin, nickel, and tin silver.


The INOVA 3D PVD reportedly provides “…superior copper sidewall coverage and ultra-low defects in high aspect ratio TSVs”. The ion-induced PVD approaches reportedly reduces the manufacturing cost of consumables for the TSV PVD process step by greater than 50 percent.


The VECTOR 3D system is reportedly able to deposit low-temperature films such as silicon nitride diffusion barriers and silicon oxide isolation and passivation layers.


The G3D photoresist strip system has been designed to quickly remove thick (20-100 micron) photoresists used in the manufacture of RDLs and pillars and to achieve residue-free strip and clean of high aspect ratio TSVs.


FPGA 3D IC Rumors


With their highly repetitive structure, FPGAs have been a natural application space for 3D IC technology although no details have been announced or published anyone on the subject. Recently there have been rumors of real work going on out there that I would be remiss I not sharing with you.


In June, in his blog on chip design magazine (link), Ed Spurling reported that although Xilinx refused to comment, “a half dozen industry sources familiar with its efforts” reported that Xilinx is developing 3D for its FPGAs. IFTLE will take it one better than that and report to you that the rumored site for Xilinx activities is Samsung. No proof here either, and no confirmation from either party just the strong rumor. Although Samsung remains deathly silent on all activities concerning 3D, trust me they will be a player.


For all the latest in 3D IC and advanced packaging technology, news and rumors stay linked to Insights From the Leading Edge, IFTLE…

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