Insights From Leading Edge

IFTLE 18 The 3D IC Forum at 2010 Semicon Taiwan

Look to Taiwan
Those that have been long time readers of IFTLE and its predecessor PFTLE know that I sometimes look at 3D IC through the eyes of someone that was part of the bumping/WLP technology explosion that occurred in the late 1990s/early 2000s. Further, if you know this history you know that while I give most of the credit for the development of most if not all of that early low cost bump/WLP technology to start ups FCT and Unitive in the USA, it was the Taiwanese who saw the power of this technology, licensed it from the aforementioned startups and put the capacity in place to make this the key technology that it is today. While fan-in WLP has evolved into fan-out WLP and copper pillar technology it has in some sense has become synonymous with “Advanced Packaging”.
Furthermore, while any commercial 3D TSV announcement is a good announcement, it is has also been clear that from the IFTLE perspective we are keeping an eye on a few key players like TSMC and Samsung because when all is said and done (a) this will be a TSV middle play and must be driven by foundries like TSMC, Global Foundries and UMC and (B) early applications will be driven by wide band memory access for memory on logic applications. So, when many of today’s 3D IC technology leaders assemble in Taiwan, it makes sense to pay attention to what they are saying. If 3D IC is to become the powerhouse technology that many of us are predicting it will, it is clear that Taiwan Inc will have to buy in and be at the forefront of leading this technology into commercialization [see PFTE 105 “Taiwanese Focus on 3D IC”, 11/06/2009 ]
2010 Semicon Taiwan 3D Technology Forum

The Semicon Taiwan 3D Technology Forum was chaired by Ho-Ming Tong, General Manager and CTO for ASE. Speakers included representatives from Yole, Nokia, Qualcomm, UMC, SIliconware, Verigy, Applied, ITRI, IME and Sematech. The next two blogs will cover significant material from this meeting.


Dr. Tong, who some say coined the term "2.5D" for the use of silicon or glass interposers with TSV, indicated that this technology “ ready to move to the next stage” Tong expects commercialization of 2.5D chip technology to take place in two years.

Tong notes that 2.5D IC should not be regarded as a transitional integration technology. 2.5D will enable packaging of chips in the 32-22 nm nodes where the fragile mechanical stability of the low-K dielectrics used in these products will require their bonding to an intermediate silicon interposer before final placement in a standard package.

Since it can also be applied in the design of high-end multi-function-integrated ICs, as in the NEC SMAFTI 3D IC design shown below, Tong contends that it will be “â??¦ developed in parallel with 3D IC as an alternative solution”

Tong believes that commercialized products made using 2.5D IC and 3D IC technologies, including smartphones and computing applications, will hit the market in the next five years. This last comment made headlines at several news outlets [ link], which Quoted Dr. Tong as saying “ Despite tremendous progress in recent years, 3D IC with through silicon vias (TSVs) still presents significant challenges in cost, design, manufacturing, test and supply chain readiness and the technology is still three to five years away from mass production”.

After checking with Dr. Tongs colleagues in ASE I have been assured that these comments were meant to indicate that widespread use in products is still 3-5 years out but that ASE stands by the recent roadmap they shared at Semicon West this summer [ see IFTLE 9 “3D In and Around the Moscone Part 1” ] which indicates that 2.5 D readiness is imminent and full 3D for wide IO DRAM / logic bonding would be coming in the 2011 timeframe.


Shan-Chieh Chien, VP of ATD at UMC called 3D stacking with TSV the “big elephant” technology for foundries. UMC, which recently announced an alliance with Elpida and Powertech [ see IFTLE 8 “3D Infrastructure Announcements and Rumors” ] commented that logic + wide IO DRAM stacking will occur in 2011-2012 consistent with the comments of his other Asian colleagues. UMC also sees a significant future for silicon interposers indicating that UMC will use their Cu dual damascene BEOL process for passive device and fine pitch RDL on these interposers.

We’ll finish up looking at the 2010 Semicon Taiwan 3D Forum next week

the CMOS Image Sensor Market

A new IC Insights image sensor market report forecast that CMOS image sensors sales will rise 34% in 2010 to $5.2 billion from ~ $3.9 billion in 2009. Between 2009 and 2014, CMOS image sensor sales are projected to increase at a 17% compound average growth rate (CAGR), reaching $8.3 billion by 2014. CMOS image sensors dominate portable systems applications, such as camera phones, webcams in notebook computers, and other embedded cameras in handheld products, but higher-speed CMOS imagers are also being aimed at automotive systems, medical equipment, and wireless video security networks.

For all the latest in 3D IC and Advanced Packaging stay linked to Insights From the Leading Edgeâ??¦â??¦â??¦


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