Remembering VLSI Japan
VLSI Japan was an outstanding technical conference which promoted the sharing of information and ideas through the 1990’s and 2000’s. My own memories bring me back to the 2000 VLSI meeting that George Harman, Len Schaper, Jan Vardaman and I attended from the US.
There were several interesting and informative 3D related papers presented at the IEEE CPMT Japan Symp this year that are worth reviewing.
3D stacks are usually joined by metallic bonding using techniques such as solder or Pb free solder bumps, Cu/Sn eutectic or Cu/Cu thermo compression bonding. Non conductive underfill can be used to fill in the space in and around the interconnections to mechanically support the interconnect. It is difficult to flow traditional underfill materials into such narrow gaps and to control material flowing out from the chip edges.
Pre applied non conductive filler (NCF) doesn’t need to flow into the small gaps or flow out over the chip edges. Lamination on structured surfaces demands a fluid nature for the NCF while a rigid material is required for dicing. This combination of properties can be obtained from materials that have temperature dependant viscosity. Such NCFs can flow into the narrow spaces between bumps and be cut with a standard dicing saw.
Pre applied NCF must be transparent, to allow viewing of alignment marks, and must not remain between the bump and the pad during bonding. Toray developed a transparent, low CTE underfill by using nm sized filler particles as shown in the figure below.
To insure that the bump / pad area is clean during bonding, the chip with NCF should be heated up to the temp where the NCF changes to a flowable liquid and then pressed into contact with the pad on the other chip in the bonder.
As an alternative solution Toray has also developed a negative tone photo NCF to insure the contact areas are free of underfill material during joining. The material flows at ~ 200 C and has a 1% wt loss temp of 300 C.
When filling TSV with Cu, the overburden is usually removed using CMP. The Cu thickness and topography requires a optimized Cu CMP process for removing the thick Cu layers. Hitachi studied friction force requirements and chemical additives for various slurries in order to develop a high speed removal process specifically for 3D processing. The table below shows both the target values and the ultimate product (HS-C935) performance.
We have discussed Japan’s ASET consortium several times in the past [ see PFTLE 104, “3D From the Land of the Rising Sun”] For the Dream Chip program Renesas and Rohm are studying thinning and pick-and-place technology for die to wafer constructions. Their specification is to achieve 10 +/- 1 µm wafer thickness stability after thinning and dicing 300 mm wafer devices.
Thinning to 10 µm requires a hard support (carrier) and an adhesive that would both be uniform and is thermally stable enough to resist degredation during grinding and backside processing.
Pick and place of these thinned chips is also a significant technical issue. They evaluated the slide-and-peel method shown below.