Current FO-WLP practitioners include licensees of the Infineon e-WLB [embedded wafer level BGA] including ST Micro, ASE, STATSChipPAC and Nanium (Qimonda Portugal) and Nepes which has licensed the Freescale RCP [redistributed chip package] technology which is similar.. Amkor and others are known to have similar products in development.
The 2010 marketplace for FO-WLP, as determined by Yole Development, is shown below.
Their technology will first be used in microcontroller (MCU) products, which require small chip size and high interconnect density. Their listed specs include: interconnect density (L/S = 15/10 Î¼m, interlayer via pitch = 50 Î¼m); chip size (5 mm Ã?? 5 mm or less) and thickness (0.3 mm) package.
The process flow involves following steps: (1) Photo PI is deposited on a Si support wafer and the patterned; (2) Cu RDL is deposited and patterned using a semiadditive process; ( design rules for Cu wiring were 15 Î¼m in width, 10 Î¼m in space, and 5 Î¼m in thickness); (3) Cu pillar bumps (CPB) with Sn-Ag solder caps were formed at relevant positions on the top Cu wirings; (4) IC chips were separately prepared with electroless Ni/Pd/Au plating on I/O pads; (5) chips attached by die-to-wafer bonding; (6) MUF (molded underfill) of the chip-bonded RDLs on the support wafer; (7) The Si support wafer was removed from the chip-bonded RDLs to form a chip-embedded resin wafer with RDLs; (8) The wafer was diced and separated into an individual packages (Before dicing, additional metallization for external terminals such as Au plating, solder ball mounting, or solder paste printing occurs).
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