Insights From Leading Edge

IFTLE 25 IMAPS Part 2 Advanced Packaging

IBM Going Fab Lite ??

Peter Clarke of EE Times is reporting that “ â??¦ IBM appears set to gradually back away from semiconductor manufacturing and to rely for its leading-edge silicon on Samsung and GlobalFoundries as foundry suppliers (link). If you are a reader of IFTLE you already knew that [ see IFTLE 8 "3D Infrastructure Announcements and Rumors”, July 2010]

“â??¦ IBM is gradually allowing itself to exit from leading-edge manufacturing at high volume. IBM appears to have joined the broad class of semiconductor companies that will never build a major wafer fab again” reports Clarke. Interestingly the last time that IBM was close to the global top 10 was in 204 when they ranked 11th.

Several Govt. types were shocked when I shared this rumor a few months ago. Clearly they shouldn’t have been. It appears that such business decisions will take what remains of IBM manufacturing prowess the way of Bell Labs, DEC and many of the other early giants in our USA microelectronics industry..

Advanced Packaging at IMAPS National

IBM Injection Molded Solder

IMS is a variation of C4NP for solder deposition on fine-pitch laminates.

The presentation on this technology is examined in detail in the ElectroIQ advanced packaging section by the presenter Jae-Woong Nah [link]: 


Alan Huffman of RTI Int presented an overview of the evolution, status and possible future for bumping /WLP which I co-authored. RTI, as you know, purchased the Microelectronics Center of NC (MCNC) ~ 4 years ago. MCNC spun off Unitive which is now owned by Amkor but “back in the day” bumping pioneers such as Iwona Turlik, Dan Mis, Glenn Rinne, Paul MaGill, Phil Deane, CJ Berry, Ted Tessier, Boyd Rogers and many others developed a plated bump process that is still used globally today. In fact the joint industry standard on “implementation of flip chip and chip scale technology” put out in 1996 by EIA/IPC/JEDEC/SEMATECH/MCNC was put together at a meeting on the MCNC campus.

Historically flip chip (or C4 as IBM called it) had been around since the 1960s but things took off commercially in 1992 after Tsukada of IBM Japan announced that they had discovered that the use of underfill allowed reliable joints directly to PCBs (i.e chip-on-board). After the commercial use of flip chip in the Motorola StarTac cell phone in 1996 the commercial use of flip chip in consumer products exploded.

It is clear today that flip chip and WLP are evolving into copper pillar bump (lower electrical resistance and inductance; lower thermal resistance; better resistance to electromigration; reduced pitch) and WL fan-out packaging (allows more IO at same pitch). A complete description of Huffmans presentation is given in a podcast interview with SST Editor Debra Vogler which can be accessed here [link].

Micron’s presentation on the next generation of PoP (package on package) indicated that there would be a required reduction in Z height of the top memory package. This in turn will require reducing die thickness and reducing the mold cap thickness.

While transfer molding is the standard mold method used in the semiconductor industry, this method has limitations when it comes to very low mold cap clearance. Issues include mold voids, bond wire sweep, and filler segregation.

Compression molding has been introduced in fan-out WLP for full wafer molding. Micron now reports that compression molding of PoP top memory packages is the most suitable molding method for structures with reduced mold cap thickness.

A key parameter for PoP packages is the warpage during reflow. Shadow Moiré was used for measuring package warpage. The study found that compression molding and transfer molding yielded equivalent package warpage when using the granular forms of mold compounds. For top PoP packages that tend to have thin mold caps, Micron reports that it is necessary to choose a mold compound with lower coefficient of thermal expansion CTE1 (below Tg) and CTE2 (above Tg) and lower cure shrinkage.

Finite element simulations indicated that the coplanarity, as well as warpage of small size packages (12mm x 12mm and below), could be controlled to under 100 μm.


We have recently reported on NEPES licensing of the Freeescale RCP (redistributed chip package) technology for fan out packaging [ see IFTLE 2, “Advanced Packaging at the 2010 Las Vegas ECTC”, June 2010].

At the IMAPS National meeting NEPES took another major step in advanced packaging when they revealed the details of their silicon module (SiP) program silicon module with Cu filled TSV and IPD (integrated passive device) LPF (Low band pass filter) integrated at the surface of silicon interposer as shown below.

The 7 mm x 7 mm Si interposer is 200 um thick. The entire package is limited to < .8 mm thickness. The spiral inductor is formed in the backside RDL layers from 8 um ED copper in low K polymer. MIM capacitors are fabricate by Al/SiO2 front end TF (thin film) processes and Cu/polymer back end processes.
The LPF shown below is fabricated from two inductors of 2.508nH, one inductor of 5.24nH and two capacitors of 1.641pF fabricated by front-end Al/SiO2.

For all the latest in 3D IC integration and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦.


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