Insights From Leading Edge

IFTLE 32 3DIC in Munich part 2

Continuing our look at presentations from the IEEE 3DIC Conference held in November 2010 in Munich.

IBM – 3D From a Server Perspective

Jeff Burns, IBM Dir of VLSI systems at Yorktown Heights, offered the perspective that 3D technology will require many changes to architecture, VLSI design, design IP, tools, technology, and manufacturing. In total this will be much larger in scope than a CMOS technology generation, rather it will be similar to the transition from bipolar to CMOS.

Burns offered the following considerations for 3D chip design:
Soitec / CEA Leti – Cu-Cu Direct Bonding

We have had extensive discussions on Cu-Cu direct bonding in the past [ see PFTLE 58, “Fisk, Buckner and Pasta on the North End”; PFTLE 26, “3D Practitioners Assemble at Ft McDowell”; IFTLE 6, "Copper-Copper and IMC Bonding Studies at 2010 ECTC” ]

We have also noted that Soitec has arrangements in place to scale up and offer for license CEA Leti technology in this area [ see PFTLE 89, “The French Connection”] .

At the 2010 IEEE 3DIC in Munich Soitec presented more details on this process. Direct bonding, unlike thermo compression or eutectic bonding, is performed at room temperature under atmospheric pressure and is based on molecular adhesion between surfaces in contact. Cu-Cu direct bonding requires flat surfaces with surface micro roughness of both Cu and oxide materials of less than 1 nm for successful bonding. Soitec indicates that standard damascene copper CMP does not provide the desired surface topography needed for a successful bonding process due to Cu pad dishing and oxide erosion. An optimized CMP process has been developed to limit the surface topography between the copper pads and the surrounding oxide dielectric. The special CMP surface preparation step leads to very smooth surfaces, the micro-roughness of both Cu and dielectric surfaces beings as low as 4-5Å. In addition the CMP renders the surfaces highly hydrophilic with the contact angle below 5°. The figure below shows that the planarization steps a) and b) are common steps in damascene BEOL while the step c) represents a specific step required for Cu-Cu direct bonding.

The figure below shows the cross section TEM images taken right after bonding (a)no annealing and after successive annealing steps at (b) 200°C, (c) 300°C and (d) 400°C during 30 minutes. Cu interdiffusion is apparent in the 200°C annealed samples, Cu grains being formed between the two layers. At higher temperatures, growth of copper grains is observed across the bonding interface.
In case of patterned Cu/oxide surfaces, oxide-oxide, Cu-Cu and Cu-oxide interfaces are formed during bonding. The bonding strength of the interfaces is shown in the figure below. The highest bonding energy is obtained for Cu-Cu interfaces, followed by SiO2-SiO2.
Bonding of 5μm Cu pads has been successfully performed with a corresponding bonding energy of more than 1J/m2 obtained upon 200°C post bond anneal. The bonding strength achieved has been sufficient to sustain post – processes such as silicon back thinning using coarse and fine grinding. Using a 5mm edge grind process, the backside thinning down to 5μm thin silicon substrate was realize with no delamination of the bond interface. Since no external force or pressure and temperature cycle is applied during bonding process, excellent alignment with minimum mechanical deformation is obtained.

Kansai Univ – “All Wet” Fabrication Technology

Some readers have pointed out that it has been several months since I gave a lesson on American idioms ( phrases which do not mean what the sum of the individual words mean). Certainly this Kansai Univ paper gives me the opportunity to do that.

As many of you know Alchimer has been reporting for several years on their “wet process” for insulation, barrier and seed [ see IFTLE 11, “In and Around the Moscone part 2”].

I have teased them in the past saying that I would indicate that their process was the only “all wet” process available. In general English usage in the US “all wet” means “completely wrong”. Searching for the original meaning of this idiom reveals it has been in use since the 1920’s although the origin of the meaning is unclear. I am sure the Kansai researchers are not meaning to describe their “fully wet” fabrication process as “completely wrong”.

The Kansai process uses electroless deposition of thin barrier layers of NiB and CoB catalyzed by the use of nano particles catalysts (Au, Pd, Pt) which are adsorbed on the SiO2 insulation of the TSV sidewalls that have been treated with 3-APS (3-aminopropyl-triethoxysilane coupling agent). A conformal electroless Cu layer can then be deposited on the barrier layer without catalyst by displacement plating.

Copper migration through the CoB and NiB barrier layers were examined by resistivity changes upon annealing. Cu / NiB was found to be stable up to 300 C and Cu / CoB up to 400 C.

Now, the community appears to have two options for a “fully wet” barrier and seed process.

ASET – 3D Architecture for Processor – Memory Integration

Ito of ASET described two 3D interconnection architectures (block and sandwich stacking) for stacked processor-memory LSIs. In the sandwich configuration, memory chips and processor chips are stacked alternately, and vertical interconnects in each PU-CHIP are divided into two groups: interconnects

for global communications and interconnects for local 3Dmemory communications. Compared with block stacking configuration, sandwich stacking architecture shows 38% fewer vertical interconnects for the same throughput and reduces power consumption by 21%.

The performances of three-dimensional stacking chips with 64- processor cores were also estimated. 3D in sandwich stacking architecture achieves twenty-times-lower power consumption of inter-chip communications than conventional 2D integration.

ASET – Copper / Polymer Hybrid Bonding

In another ASET presentation Aoki of ASET detailed their studies on copper / polymer hybrid bonding technology. We have seen copper / polymer bonding previously from both IMEC [ see PFTLE 10, “3D IC at the 2010 IEEE IITC” ].

For such bonding technology the surfaces of the metal and polymer must be globally flat. ASET applied a single damascene process for forming the hybrid bonding surface. To reduce surface-step height caused by copper dishing, a technology to co-planarize both the copper and polymer was developed. Polybenzoxazole (PBO) was used as the polymer for sealing bumps because it features positive-tone photosensitivity, high chemical resistance, and high thermal stability.

PBO polishing rate can be controlled by optimizing the PBO cure temperature. From the figure below you can see that curing the PBO at approx.. 280 C results in a very small step height ( less than 50 nm) which allows a globally planarized 200 mm wafer to be obtained.
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