A few weeks ago Mark Durcan, COO of Micron, at the IEEE ISS meeting in Half Moon Bay, commented that Micron is ”sampling products based on TSVs” and that “Mass production for TSV-based 3-D chips are slated for the next year or 18 months” [see IFTLE 33, “ Micron 3D Response, Sematech Standards, Leti 300 mm Line” ]
Now, Micron has announced that it is using TSV technology to address the longstanding problem referred to as the "memory wall". [see “Micron to reveal tech it says increases chip speed 20-fold” ]
For those that are interested, the seminal paper in the area appears to be “Hitting the Memory Wall: Implications of the Obvious” by Wulf and McKee in the March 1995 issue of Computer Architecture News which can be read here [link]. It presents an interesting discussion of the bounds on processor performance imposed by memory performance. Historically, processor performance has improved by about 60% per year, whereas the corresponding improvement in memory access time has been less than 10% per year. Latencies are dominated by DRAM access times which has changed VERY slowly over last 20 years. DRAM performance is constrained by the capacity of the data channel that sits between the memory and the processor. No matter how much faster the DRAM chip itself gets, the channel typically chokes on the capacity. Systems are not able to take advantage of new memory technologies because of this latency issue.
Brian Shirley, vice president of DRAM Solutions at Micron claims that their “hyper memory cube” technology “â??¦offers a 20-fold performance increase while reducing the size of the chip and consuming about one-tenth of the power”. They reportedly accomplish this by stacking memory on top of a controller layer (shown in the Micron fig below as logic layer) and connecting with TSV. The “wide bus” from the controller layer to the CPU is reportedly “hugh” (possible 512 bits ??)
Shirley commented “Performance needs are most dire in networking and cloud computing. One-hundred gigabit Ethernet routers and switches and cloud computing servers require everything they can getâ??¦â??¦this is our way of giving them a fire hydrant.”
They hope to see the memory cube technology in server and networking markets as early as 2012, with significant volumes in 2013, and could then start to work their way toward the consumer space in 2015.
The overall concept of the control layer reminds IFTLE of the structures that Bob Patti of Tezzaron has been showing for the past 5 years (see below)
Although Intel will not confirm, rumors persist that the key to Ivy Bridge’s reported performance is its stacked memory and silicon interposer [see: “Intel puts GPU memory on Ivy Bridge” ]
Rumors are that Ivy bridge will use LPDDR2 memory, possibly with a speed of only 1066MHz, and that memory stacking technology could bring it up to 1GB. The memory is then stacked upon a silicon interposer. The reason a silicon interposer is essential for Ivy Bridge is the large width of the low-power memory. Since 512 bit brings with it high pin and trace counts, which would require more layers and increase cost. The interposer decreases the required on chip layers and reducing the overall cost.
IFTLE has taken the rumors a step further. IFTLE thinks it is possible that the following patent application [ see: US 7,841,080 B2 ] entitled “Multichip Packaging using an Interposer with Through Vias” which describes having a CPU on an interposer with stacked DRAM and a voltage regulator may be related to the Ivy Bridge implementation.
Ivy Bridge may be Intel’s first product introduction with TSV. We’ll know for sure one they release the information and/or once Ivy Bridge is released and analyzed by someone like Chipworks.
One additional comment. It is likely that the use of an interposer (if true) reveals that Intel agrees with Xilinx [ see: IFTLE 23, “Xilinx 28 nm Multidie FPGAâ??¦” ] and indeed true 3D stacking (memory directly bonded to logic circuits with TSV) is not yet available and/or ready for “prime time” â??¦.yet.
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