Samsung, who first revealed 3D TSV stacked memory prototypes in 2006, announced 40nm 8GB RDIMM based on four-gigabit, 1.5V, 40 nm DDR3 memory chips operating at 1,333MHz and 3D TSV chip stacking technology in Dec of 2010. Samsung claimed the 3D TSV technology saves up to 40 percent of the power consumed by a conventional RDIMM and improves the memory chip density. This DRAM chip was suggested for servers to reduce power consumption and save space. They said Samsung planed to apply the higher performance and lower power features of its TSV technology to 30nm-class and finer process nodes.
At the recent plenary lecture of Dr Oh-Hyun Kwon, President of Samsung ‘s semiconductor business, at IEEE ISSCC 2011 (Int Solid State Circuits Conference), he announced the development of wide I/O 1 Gb DRAM. This memory is reportedly aimed at mobile applications like smartphones and tablet computers. Kwon reports that the 3D TSV architecture will be implemented on their 50 nm node DRAM technology. In related disclosure at the ISSCC Samsung researchers offered more details about the wide I/O memory chip in their technical presentation entitled “ A 1.2V 12.8 Gb/s 2 Gb Mobile Wide I/O DRAM with 4 x 128 I/O Using TSV Based Stacking”.
Previous generations of mobile DRAMs used a maximum of 32 pins for I/O. The new wide I/O solution which has 512 I/O (up to 1200 total) pins can transmit data at a rate of 12.8-Gbytes per second resulting in a significant improvement in processing power. In addition it reportedly reduces the power consumption by 75% by reducing load capacitance. It is expected to replace low power DDR2 DRAM (LPDDR2) which runs at approximately 3.2-Gigabytes per second according to Samsung.
Following this wide I/O DRAM launch, Samsung is aiming to provide 20nm, 4Gb wide I/O mobile DRAM sometime in 2013. Traditionally "wide" parallel interfaces have been more expensive to manufacture and package. Samsung claims, however, that its 1Gb memory chip with wide bandwidth can be installed instead of a larger amount of smaller chips which results in reduced costs and higher performance.
The SEMI ISS meeting (Industry Strategy Symposium )[link] is an annual January event in Half Moon Bay, CA where industry experts and other economic prognosticators make predictions about the upcoming year for the semiconductor industry. [ see PFTLE 121, “IC Consolidation, Node Scaling and 3D IC” for last years coverage]
Bill McClean of IC Insights pegged the 2010 semiconductor market at $313.8B, an increase of 32% over 2009. He is predicting a 10% increase for 2011. He claims a 98% increase in capex occurred between 2009 and 2010 and projects a 6% increase in 2011 to $53.8B. The semiconductor materials market saw a 24% increase between 2009 and 2010 to $42.9B and will see a 8% increase in 2011.
When looking at capex by region (2011 projected vs 2005) we see NA holding constant, Japan and Europe going down while Taiwan and Korea are going up.
10 companies held 85% of the worlds 300mm capacity in 2010.
When looking at growth by geographic region IBS sees China becoming 50% of total consumption by 2012-2013. This means foreign supply will remain a significant portion (ca. 90%) of consumption out into he future (2015)
Thus at 28 and 22 nm taking cache off chip into a 3D technology may be a viable economic option.
For all the latest in 3D integration and advanced packaging stay linked to IFTLEâ??¦â??¦.
Hope to see many of you at the IMAPS Device Packaging Symposium in AZ next week !