Brandon Prior of Prismark Partners pointed out that 3D TSV will be competing with the incumbent mobile phone 3D packaging solutions, PoP and PiP. PoP lacks the ability to interconnect more than 200 – 300 I/O from memory, but offers ease of test. TSV will offer higher speed and many more connections .
James Malatesta of Micron presented his perspective on the work of JEDEC committee JC63, the multichip package committee. First PoP changed the landscape as logic suppliers realized that standard top package “memory modules” were requuired for multiple industry supply sources. He also gave an interesting comparison of low power DDR2 [LPDDR2] vs the wide IO TSV technology that is expected to replace it [see IFTLE 40, “Samsung Wide I/O DRAM for Mobile Productsâ??¦”]
Sitaram Arkalgud, Director of Sematechs 3D IC program described their current acivities on the U Albany campus. They view their role as helping to :
• Develop robust technology solutions
• Assist member company implementation
• Drive convergence of the materials/equipment solutions
Sematech has examined the current 3D TSV tool set and come to the following conclusions:
In Matt Nowak, Sr Director at Qualcomm, presentation he asked the question “since the key attributes of 3D IC are: (1)Performance enhancement; (2) Improved power efficiency; (3) Form factor miniaturization and (4) Cost reduction can 3D IC take the place of scaling as CMOS technology appears to be slowing down or stalling out” . He concludes:
• If performance enhancement and power reduction are the primary motivation, then TSS opens new opportunities for innovative architectural and SW solutions with major improvements possible. But requires Pathfinding and risk taking.
• If form factor miniaturization is the only motivation, then yes
•If cost reduction is the primary motivation, then generally the answer is no. However, TSS can provide cost reduction within a window of time for large die sizes on leading edge nodes.
• If cost improvement from CMOS scaling diminishes in future nodes (due to Adv Litho and FEOL cost), then the window of opportunity for TSS increases.
Taiji Sakai of Fujitsu made a strong case for why low pitch bonding has moved to copper pillar bumps and wants to move to direct Cu-Cu bonding . The limiting factor preventing that move right now is time/temp required.
The 3D panel session was put together by Qualcomm’s Matt Nowak and moderated by Applied Materials Paul Siblerud.
Interposers failing thermal cycling tests
It was the fall of 2009 that everyone became aware of copper protrusion (or pumping ) as a reliability issue in 3DIC technology. This was discssed extensively in last years IMAPS DPC[ see PFTLE 125, "3D IC at Ft McDowell"] . In the last 12 months many major players confirmed the issue, solutions were proposed and our fears were allayed as to this being a showstopper for 3D IC technology [see IFTLE 6, "Cu-Cu and IMC Bonding Studies at 2010 ECTC"; IFTLE 30, "IEEE 3DIC 2010 in Munich" and IFTLE 34, "3D IC at the 2010 IEDM" ].
The rumors going around at this years IMAPS-DPC were concerned with interposers reportedly failing thermal cycling (TC) reliability tests. Word has it that when the interposers are populated with unequal size or thickness silicon chips or stacks the stresses generated on the interposers is so significant that it causes interposer fracture. I asked the panel, which I was part of, to comment on these rumors. Ron Huemoeller, VP of 3D packaging for Amkor answered that this indeed was the case, that they had seen such problems in the Xilinx scaleup. The good news from Ron is that they were able to engineer around these issues. FYI, recall that the Xilinx interposer is 100 um thick. It is unclear from the current rumors at what thicknesses (chips, stacks and interposers) these issues are seen.
Underfill with Interposers
Underfill has been around since Tsukada told us that they allowed bumped chips to reliably be used on laminate substrates back in 1992. Thus, one would think that underfills would not crop up as a problem in todays 3D technology. However, you must recall that for something like the Xilinx structure [see IFTLE 28, "Xilinx 28 nm Multidie FPGA..." we are talking about microbumps on 45 um pitch, not your typical 150 um solder bumps on 400 um pitch. Amkors Huemoeller comments on the 3D panel that the underfill process took a year get to a manufacturable state. Hopefully the underfill supplies now have the formulations set and can recommend solutions that can be implemented much quicker than that.
EMC 3D closing downâ??¦â??¦.
Paul Siblerud of Applied Materials gave the conference pre notification that EMCD 3D consortium members have concluded that they have met their goals and will be closing this summer. Their last presentation as a group is expected to be at Semicon this July.
Memory Stack Usage coming soon
Huemoeller offered the following Amkor roadmap for memory stack usage:
At the GBC, Suresh Ramalingam of Xilinx discussed the key role of supply chain collaboration. The FPGA is basically a programmable SoC of logic, memory and analog circuits.
Customers were asking for more logic capacity, more high speed transceivers, more processing elements and more memory and Xilinx was faced with the reality that yield of the devices is directly proportional to device size. Rather than try to interconnect smaller devices on a PWB or MCM, which did not offer enough I/O and resulted in high latency and high power usage, their preferred solution was to connect FPGA “slices” on a silicon interposer which offered massive low latency interconnect (10K routing connections between slices with ~ 1ns latency) and low power consumption. They claim this gives them a 1.9X advantage over their nearest competitor.
The 28nm Virtex-7 SSIT will reportedly use TSMC fabricated 100µm thick silicon interposers with 10 – 12 µm Cu TSV and 65nm interconnect. The micro-bumps are Cu-SnAg alloys at 45µm pitch.
Mike Kelley, Sr Dir of Advanced 3D Packaging for Amkor indicated that Amkor bumped the FPGA chip wafers whereas the interposers from TSMC arrived bumped and ready for assembly.
Amkor offered the following process flow for test during assembly :
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