JEDEC has recently summarized their ongoing standards development work related to 3D-ICs. The following JEDEC committees and task groups are engaged in developing 3D-IC standards:
- the Solid State Memories Committee (JC-42) has been working since 2008 on definitions of standardized 3D memory stacks for DDR3 . Future DDR4 standards will be implemented with 3D input.
- the Multiple Chip Packages Committee (JC-63) is currently developing mixed technology, pad sequence and device package standards.
- a Low Power Memories Subcommittee (JC-42.6) task group is developing standards for Wide I/O Mobile Memory with TSV interconnect stacked on SoC Processors.
- the Silicon Devices Reliability Qualification and Monitoring Subcommittee (JC-14.3) is working on reliability interactions of 3D stacks and has released JEP158: 3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Understanding and Evaluating Reliability Interactions.
- reliability test methods developed by JC-14.1 and JC-14.2 and quality documents developed by JC-14.4 are applicable to 3D-IC packaged and unpackaged evaluations and qualifications.
- the Mechanical Standardization Committee (JC-11) has been working since 2010 on Wide I/O Mobile Memory package outline standardization, including a task group focused on design guide creation.
JEDEC invites interested companies and organizations to participate.
I have previously expressed my concerns over the lack of transparency in JEDEC standards due to their self imposed rule forbidding revealing authorship [companies and /or individuals] up the standards. [ see PFTLE 128 “3D IC Standardizatio Begins” ] Those concerns still stand.
Hynix Semiconductor Joins SEMATECH’s 3D Interconnect Program
Hynix the last top 5 DRAM to not have announce plans for 3D IC has become a member of SEMATECH’s 3D Interconnect program. Dr. Sung Joo Hong, Head of the R and D Division of Hynix Semiconductor commented that "3D integration offers a path for higher performance, higher density, higher functionality, smaller form factor, and potential cost reduction,â??¦.by joining SEMATECH’s 3D Interconnect program and collaborating with industry-leading partners, we expect to play a critical role in accelerating the commercialization of wide I/O DRAMâ??¦” Hong reported that Hynix and SEMATECH will address the commercialization challenges facing the industry as it commercializes wide I/O interface structures using TSVs in high volume manufacturing in the next two years.Hynix will be working with IBM, GlobalFoundries, Toshiba, Samsung, Applied Materials, Tokyo Electron, ASML and Novellus as part of the SEMATECH program.
IC Power Rankings from IC Insights
Semiconductor industry capital spending is becoming more concentrated, with a greater percentage of spending coming from a shrinking number of companies. As a result, IC industry capacity is also becoming more concentrated, and this trend is especially prevalent in 300mm wafer technology.
IC Insights has created a “Power Rating” which is determined by each company’s 300mm wafer capacity and its rank in capital spending.
Overall, IC Insights believes that the top-10 companies in the “Power” ranking will be the primary drivers in adding capacity over the next few years. GlobalFoundries and TSMC get a boost from their currently aggressive capital spending plans and are very likely to add a significant amount of 300mm capacity over the next few years. Among companies ranked between 11 through 22 Renesas, IBM, TI, ST, and Fujitsu are moving to or continuing with a fab-lite strategy. These five companies appear unlikely to add new 300mm capacity in the future. Powerchip, SMIC, ProMOS, Winbond, and Xinxin appear limited by financial where-with-all (e.g.,) or a lack of desire (e.g., Rohm and Panasonic) to add significant amounts of 300mm capacity to produce leading-edge digital ICs.
With only ten major players in the 300mm capacity space, the customer base for leading-edge IC production equipment has become very narrow. It is likely that IC equipment and materials suppliers will be focused on these 10 companies in the future.
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