50 is a big round number that means IFTLE is nearly a year old here on the SST website. From the data I’ve been shown recently, we have steadily built up readership since last spring to the point that we are now getting ~10,000 readers /month to this site. â??¦â??¦.A sincere thank you for your interest.
As you know the Insights From the Leading Edge, or IFTLE as I like to call it, focuses on 3D integration and other advanced packaging technologies. We try to keep you abreast of where and when they are introduced and what kind of impact they will have on this field of Microelectronics that we have chosen to be a part of.
I just spent my 62nd birthday with my granddaughters in Houston. This gives me the opportunity to slip in another picture of the girls which I have already explained I get to do because this is my blog.
Miss Hanna (left) and Miss Madeline (right) informed me that 62 meant I was an old man. I told them that with age came experience and with experience came wisdom so they should listen to their old grandpa. They both just giggled not having a clue what I was talking about. Certainly we all get older, but do we all get wiser ? I’ll leave that as something for you to think about.
On my birthday I noticed that Dr Morris Chang had a few words to say in the China Post. Chang, Chairman and founder of TSMC and winner of the 2011 IEEE medal of honor, announced that TSMC is now capable of 28 nm and is focusing on 20 nm. He also announced that Moores Law would meet its demise by 2020 at which point we simply would not be shrinking transistors any more. These were strong words from a man who runs the worlds number one IC foundry. [Link] He pointed out that in the future, more attention will be paid on packaging solutions and printed wring boards which had not yet met their physical limits. For TSMC he pointed specifically to MEMS, image sensors, photovoltaics and LEDs.
At a TSMC forum April 5th in Santa Clara Chang indicated that the PC and cell phones have been the big drivers for the IC industry but that now “ a third ‘killer app. – mobile products (smart phones and tablets)” was ruling things.
Addressing 3D, Chang indicated that TSMC has poured "significant R and D" into 3-D chips using through-silicon vias (TSVs). The company calls it as a paradigm shift called "systems-level scaling," .
Looking at the 450 mm waer question he noted that "There are still a lot of challenges for 450-mm," and that TSMC “ would build a 450-mm pilot line in the 2013-2014 time frame, followed by production in 2015-2016” with “the intercept point is 20-nm”
Some might think that these concepts were put together by his underlings who are assigned to stay on top of technology, but maybe not. Chang has always been keenly interested in both the technology and the business aspects of our semiconductor industry since his early days at MIT.
My own experience with Dr Chang came about 12 years ago when I was in Taiwan introducing BCB for redistribution and bumping. We were visiting TSMC when our host informed us that the Chairman would be joining our meeting because he wanted to understand what all the of the interest in bumping and redistribution of chips was about. He personally took us out to lunch in order to have more time to absorb technical. He explained that he knew that bumping technology was being used by the mainframe players but had recently been hearing that it was moving into consumer products. A few years later, TSMC became the first foundry to put bumping capacity in place (2001). â??¦â??¦Morris Chang – without question is a wise, old man.
Intels new “3D technology”
As if we didn’t have enough trouble explaining that 3D IC technology has nothing to do with wearing glasses to watch your new TV, some reporters in the industry are now calling the Intel;tri gate transistor a “3D chip” [link] . Actually this is not something new, Intel first announced their tri-gate structure in September 2002 and indicated that they were readying it for introduction at 32 or 22 nm, which is exactly what they are doing.
This concept here is explained very nicely by Greg Crowe [link]. “Here’s the basic idea. A transistor has power flowing through it from the source end to the drain end. The presence or absence of a current is determined by the voltage level of the gate that bridges the two. The major problem with the traditional setup involves signal loss resulting from the fact that the gate only contacts the source and drain on one surface. A tri-gate transistor has three gates that make contact on three sides at once, effectively tripling the amount of surface through which electrons can travel. This produces less data leakage and uses less power than the older design.”
Intel has indicated that this will deliver a third more processing speed, and about half as much power consumption. This means that at 22 nm Intel can pack in twice as many transistors in about the same-sized chip for the same power usage, which operate a third faster – effectively giving us about 2.5X the processing power for the same power consumption.
There are those asking how this will affect the introduction of 3D IC. Only Intel knows for sure, but I can tell you that these faster ICs will be looking to access memory even faster than they do now so my guess would be that memory on logic will be needed even more.
My previous thoughts were that TSV would show up in the 22 nm Intel "ivy bridge" [see IFTLE 38, "..of Memory CUbes and Ivy Bridges…"] with both stacked memory and interposer. We will see whether that is still true.
So thanks for your continued readership and if you continue to be interesred in 3D IC integration and other advanced packaging, stay linked to IFTLE !