Insights From Leading Edge

IFTLE 51 2011 IEEE IITC 3D Highlights, and IEEE ECTC OSAT Preview

The annual IITC, sponsored by the IEEE Electron Devices Society was held a few weeks ago in Dresden. Ehrenfried Zschech of the Fraunhofer , John Iacoponi of GLOBALFOUNDRIES and Takeshi Furusawa, of Renesas lled the program committee.
The conference which was instituted in the mid 1990’s was the premier show dealing with issues of on chip interconnect, especially low K. In recent years it has shifted some focus to 3D integration [ see PFTLE 37, “IITC on the 3D Integration Bandwagon” and IFTLE 10 IFTLE 10 “3D at the IEEE IITC”.

In this years conference Yann Civale from IMEC shared technical details on the “Thermal Stability of Copper Through Silicon Via Barriers during IC Processing”. The IMEC via-middle process flow results in several high temperature processing steps after TSV fabrication, including a final device wafer sintering step, generally in the 400°C range. As you may recall this was introduced to reduce the impact of copper extrusion [ see PFTLE 125, “ 3-D IC at Ft McDowell” and IFTLE 34 “ 3D IC at the 2010 IEDM”] Thus, it is essential to determine the stability of the TSV Cu-barrier at these temperatures to ensure a reliable integration of 3D TSV in CMOS wafers. IMEC reports that 5nm Ta barriers are thermally stable, while Ti-barriers require thicknesses above 5nm to guarantee their thermal stability.

Paul Marchal of IMEC presented a “Technology Roadmap and Status” for 3D IC. Marchal indicates that 3DIC technology is now becoming available, that co-optimization of design and procfess technology are required and that one of the remaining hurdles remains mechanical and thermal stress.

The thermo and Thermomechanical challenges for DRAM on Logic are shown below.

Interestingly scaling of the TSV diameter will strongly reduce the KOZ (keep out zone) as shown below.

The combination of microbump and underfill has been identified as the major contributor for stress on thinned die as the shrinking underfill bends the thin die around the microbump. Agreement salso needed on exchange formats and models are required.
Projections for 2015 include:
Silicon wafer thickness : preferably 50 um and holding due to stress and thermal issues.
Microbump pitch : 20 um and decreasing for improved electrical specs
SV dia / pitch : 5-3 um / 20/10 um and decreasing dia scaling to decrease KOZ, results in AR ~ 20
Armin Klumpp Peter Ramm and co workers at Fraunhofer EMFT presented their information on  “Reliability testing and Failure Analysis of 3D Integrated Systems“. Their 3D-integrated reliability test chip is a 3-level-stack with a modular layout so several types of stacked devices can be realized, numbered type 1 – 4 with basic functions of the “Bottom”, “Middle” and “Top” layers in the figure below. The larger size of the Bottom chip allows access to the measurement pads, independent of the number of stacked layers. The medium chip having TSV’s and can be tested already in the stage of thinned silicon with the appropriate metal layers on front and back side (type 1). In combination with the bottom chip daisy chains can be realized that include TSVs and assembly pads (type 3). Medium chips with no TSVs, can be tested (type 2), to be able to distinguish between TSV and assembly pad parameters. Type 2 and type 3 are available in parallel as soon as the medium chip is assembled on the bottom one. Adding the top chip forms a three level stack (type 4) with daisy chains including TSVs and two levels of assembly pads. The medium chip serves in this case as feed through for electrical signals. The top chip shortens the electrical path to form a daisy chain consisting of at least two TSVs. The chip lay-out contains several elements including Kelvin structures, DC and RF test structures, daisy chains and TSV’s with dimensions varying from 3-50 um. 3D-integrated test chips were fabricated by application of Fraunhofer EMFT´s TSV SLID technology. The applied 3D TSV process is based on inter-metallic compound (IMC) bonding and TSV formation before stacking. For reliability testing, termal cycling (-55 C° to +150 °C) was performed and additional analysis was done by cross sectioning and plasma-FIB.
ECTC Preview
Remember when we all rushed to ECTC anticipating the latest advanced packaging presentations of IBM, Intel, Bell Labs and NEC, Hitachi and Fujitsu ? Well times have changed, and over the last two decades the pendulum has swung towards the OSATS and I think it’s fair to say that Amkor, STATSChipPAC and ASE are now producing more than their share of outstanding papers at every ECTC conference.
As an example, here is the list of papers that Akor is scheduled to present next week in Orlando.
"Cu Pillar and µ-bump Electromigration Reliability Comparison with High Pb, SnPb, and SnAg Bumps" presented by Ahmer Syed

"Advanced Coreless fcBGA Package with Embedded High-Dk Thin Film Decoupling Capacitor" presented by GaWon Kim

"Next Generation Fine Pitch Cu Pillar Technology – Enabling Next Generation Silicon Nodes" presented by Curtis Zwenger and Mark Gerber of TI

"Issues in Fatigue Life Prediction Model for Underfilled Flip Chip Bump" presented by Ahmer Syed

"Crack Initiation and Growth in WLCSP Solder Joints" presented by C.J. Berry

"A Study on an Ultra Thin PoP using Through Mold Via (TMV) Technology" presented by Akito Yoshida

"Characterization of Intermetallic Compound (IMC) Growth in Cu Wire Ball Bonding on Al Pad Metallization" by SeokHo Na

Hope to see some of you next week in Orlando. For all the latest in 3D integration and advanced packaging stay linked to Insights from the Leading Edgeâ??¦â??¦..


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