Insights From Leading Edge



IFTLE 52 3D and Adv Pkging at ICEP 2011 and reschedule of 2011 3DIC (Japan)

ICEP
The ICEP [ Int Conf on Electronic Packaging] is put on by JIEP (Japan Institute for Electronic Packaging) It is usually held in April every year during cherry blossom time in Japan. I recall that in 1998,when the meeting was known as IMC/IEMT Rao Tummala and I were in attendance. At the “gala reception” we were coerced into joining the entertainment on stage and then I, as the junior member, was further coerced to dress up in a “happy coat” which my granddaughters now know as grandpa’s samuri outfit. (see below).
At this years conference, John Lau of ITRI gave an excellent invited review on the origins, status and future prospects for 3D IC which includes a must have list of 140 references in the field including his observation that Shockley, inventor of the transistor, actually patented TSV in 1958.
Lau astutely observes “â??¦ using a passive interposer to integrate a few “bullet proofed” chips together (like a MCM) want and are used to doing. The passive interposer becomes the most effective 3D IC integrator. It could be very low cost because we don’t have to dig and fill the holes on the active die. Also we don’t have to thin and metallize the active die. Furthermore we don’t have to temporarily bond and debond a supporting wafer to the active wafer.”
In another paper Lau and his ITRI colleagues discuss the feasibility of 3D IC for system in package structures. In their test vehicle a assive interposer supports a 4 memory chip TSV stack, an electrical test chip, a thermal test chip and a mechanical test chip to measure stress and warpage . The interposer is 12.3 x 12.2 mm and 100 um thick. The TSV diameter are 10 and 15 um on 40 And 50 um pitches.
TC Chang from IRTI detailed the use of thermocompression bonding for the joining of Pb free microbumps on 20 um pitch. Solvent and plasma are used to remove the flux residue between he microgaps and a capillary underfill with 0.3 um filler (Namics) is used to fill the gaps.
NEC, Univ Tokyo and ASET reported on the formation of power regulators (buck converters) which consists of a CMOS LSI including active components and an output filter embedded in the Si interposer.
Koyanagi and co-workers at Tohoku University described their development of 5 um diameter backside TSV technology. Tohoku is located very close to the site of the Tsunami devastation so I’m sure we all wish them well as they bring their University and their 3D activities back up to speed.
To develop 5 um backside TSV the chip was supported on a glass or silicon support substrate and thinned down to 15 um by grind and CMP. ~ 1 micron SiO2 was deposited as an isolation layer / hard mask . The TSV were created with Bosch process and then lined with SiO2 (500 nm) . Etching parameters (shown below) were used to control the scallop. The bottom of the insulated TSV were opened by SiO2 etching using the thicker backside oxide layer as partially sacrificial mask for the etching.
2011 IEEE 3DIC
The IEEE 3DIC meeting which was scheduled for Tokyo this fall has been moved to Osaka in Jan 2012 due to the tsunami / nuclear disaster that Japan has been recently dealing with. The submission deadline for abstract is September 30, 2011.
For all the latest in 3DIC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦.

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