Very little technical detail was released at that time, presumably because of the rumored exclusivity TI was given as part of the joint development program. Full technical details were to be withheld a year till the 2011 ECTC conference, which just occurred this past week. We’ll be covering the overall ECTC technical content over the next few weeks, but I first wanted to focus on the Amkor / TI paper “Next Generation Fine Pitch Cu Pillar Technology – Enabling next generation Silicon Nodes” since we have all been waiting a year for the details which were presented by Curtis Zwenger (Amkor) and Mark Gerber (TI).
Flip chip technology has traditionally been driven by electrical performance and package miniaturization, with application processors being the primary drivers for mobile phone applications. Traditional solder or Cu Pillar interconnect pitches have been 150um to 200um for both low and high end flip chip applications. Today wafers are routinely bumped at 140 – 180 um pitch with 90 um solder balls in area array. Advanced silicon nodes create challenges to fine pitch (less than 100 um) flip chip interconnects and the corresponding substrate technology. Use of low-k dielectrics, thinner ICs, and package warpage are challenges.
Migrating from wire bond interconnects to area array flip chip requires a redistribution layer be added to the device to provide the required interconnection pattern. Fine pitch flip chip is compatible with existing in-line and staggered wire bond pad patterns, avoiding the cost for redistribution of the circuit on the die. Amkor claims that 80 percent of their internal studies on converting existing area array flip chip designs to fine pitch designs resulted in a lower cost substrate due to metal layer count reduction and/or body size reduction.
Fine Pitch Cu Pillar Test Vehicle
The qualification vehicle was a 559 bump chip on 50 um pitch and a 0.4 mm BGA array coming off the substrate ( 12 – 14 mm PoP body size).
The primary process development challenge centered on the flip chip attach and bonding processes. For Cu Pillar flip chip with pitches less than 100um, the placement accuracy of the die to substrate is critical to help ensure a high yielding manufacturing process. Amkor found that thermal compression bonding was best suited for fine pitch copper pillar products. Thermal compression bonding, used in conjunction with a pre applied underfill (NCP = non conductive paste). The process flow is shown in the figure below.
It is important to control the height of the die in relation to the substrate. Pillar height, substrate capture pad height, and die thickness must be controlled to help ensure a stable process. For an over bonded Cu pillar die the solder cap can be squeezed out the sides of the joint causing solder shorts between the pillars.
The new fine pitch packages were put through standard JEDEC MSL L3 260 ºC un-biased package reliability tests including temperature and humidity, unbiased HAST, temperature cycle level B and high temperature storage tests as well as board-level reliability (BLR) testing (drop and temperature cycle) and biased component-level (CLR) reliability testing.
Rumors are that Amkor is adding additional fine pitch Cu Pillar capacity for TI and that the process is being transferred to TI who will be putting additional capacity in place for some of their own products. TI has indicated that they are open to licensing the fine pitch Cu pillar technology to others.
For all the latest on 3D IC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦..