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IFTLE 54 2011 ECTC and Glass Interposers

Greater than 1000 attendees enjoyed the 2011 Electronic Component Technology Conference [ECTC] in Orlando FL. 342 of 641 submitted abstracts were selected by the program committee for presentation.

The technical focus continued to be on 3D integration which included  6 sessions and several dozen poster presentations. There were also a large number of submissions dealing with electromigration, the issues and reliability of fine pitch 3D micro joints, and numerous new advanced packaging proposals. We will begin by looking at TSMC and Ga Tech presentations on glass interposers and take a look at the other topics in the following weeks.

Glass Interposers

Glass is being examined as  a low cost alternative to the Si interposer. Compared to organic substrates ( ca 15 ppm), glass (3.2-9 ppm) has better CTE match to Si (2.3 ppm). Glass also exhibits excellent surface flatness, dimensional stability, high electrical resistivity and the availability in thin and large panels. The main challenges for glass interposers include:

- the ability to form ultrafine pitch TSV at high speed
- thermo-mechanical reliability of copper filled TSVs in glass
- thermal conductivity of glass (Si>glass>PWB)

Although the fracture strength of a defect-free glass is high, it decreases dramatically with any surface or bulk defects, which could be caused by processes such as etching, cutting, drilling, or metal deposition.

TSMC reported on test interposers which consisted of 100 um diameter TSV drilled in 360 um thick glass substrates on 200 â???? 500 um pitch. The test structures had 1,521 I/O in area array on a 40 x40 mm substrate.

They found that glass fracture strength decreases with decreasing TSV pitch. Higher via density leads to less cross section area and lower strength is observed. Data scatter is reportedly  due to structural defect s inherent in the glass after processing. They found that coating the glass on both sides with a â????thin film materialâ???? (which appears to be PI) resulted in marginal improvements (10-20%) in glass fracture strength.
 ANSYS modeling was employed to simulate the material deformation for stress and strain analysis when the package is simulated under temperature excursion. A flip chip BGA with BT substrate was modeled for comparison purposes. Solder material, die thickness, glass size, glass thickness, via diameter, via pitch, PI coating thickness and CTE of glass were all examined as variables. When replacing the BT laminate with glass ( CTE of 8..3 ppm) the deformation of the package increases from 0.15 to 0.27 mm due to the larger CTE mismatch between substrate and PCB. Due to reduced CTE mismatch between die and glass, the maximum stress is reduced by approximately 38% when compared to the organic substrate. The most significant factor appears to be die thickness. Thick Si die introduce higher stress on glass substrate, owing to its increased rigidity which restricts the glass and/or die from deforming to relieve the stress. The CTE of the glass is also important since higher CTE glass induces higher stress to the die. They found that a medium CTE (ca. 8.3 ppm) glass is better for lower die stress.
The substrate serves as an interposer between low CTE Si die and high CTE PCB. Glass with higher CTE reduces BGA balls stress but is harmful to the Si die and vise versa. Overall, from the TSMC simulations, the medium CTE glass substrate at around 8.3 ppm is demonstrated as the optimal choice for the package structure. Some of the other factors, such as glass thickness, via diameter and PI thickness do not seem to play a significant role to affect the stress of the die, BGA ball or glass.
A Georgia Tech PRC consortium is also looking at glass as an interposer candidate . The glass substrates (either borosilicate [CTE = 3.8 ppm]or â????high CTEâ???? [8.5 ppm] glass) are 180 um thick with 15 um thick polymeric coatings on top and bottom similar to the TSMC construction. The 30 um TSV are either filled or conformal. Panel sizes are currently 150 mm.

The conformal TSV exhibited similar electrical performance as the filled TSV but are expected to show better thermo-mechanical reliability behavior. Stresses in the polymer layers are higher for thicker layers as expected.
Electrical properties of the glass interposer were extracted from measured and simulated data on ring resonators [dielectric constant ~ 4.8 and loss tangent ~ 0.002 up to 19.4 GHz. Low insertion loss of less than 0.15 dB at 9GHz was measured for the TPVs in the thin glass interposer.
For all the latest in 3D IC and advanced packaging stay linked to Insights From the Leading Edgeâ??¦

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IFTLE 54 2011 ECTC and Glass Interposers

Greater than 1000 attendees enjoyed the 2011 Electronic Component Technology Conference [ECTC] in Orlando FL. 342 of 641 submitted abstracts were selected by the program committee for presentation.

The technical focus continued to be on 3D integration which included  6 sessions and several dozen poster presentations. There were also a large number of submissions dealing with electromigration, the issues and reliability of fine pitch 3D micro joints, and numerous new advanced packaging proposals. We will begin by looking at TSMC and Ga Tech presentations on glass interposers and take a look at the other topics in the following weeks.

Glass Interposers

Glass is being examined as  a low cost alternative to the Si interposer. Compared to organic substrates ( ca 15 ppm), glass (3.2-9 ppm) has better CTE match to Si (2.3 ppm). Glass also exhibits excellent surface flatness, dimensional stability, high electrical resistivity and the availability in thin and large panels. The main challenges for glass interposers include:

- the ability to form ultrafine pitch TSV at high speed
- thermo-mechanical reliability of copper filled TSVs in glass
- thermal conductivity of glass (Si>glass>PWB)

Although the fracture strength of a defect-free glass is high, it decreases dramatically with any surface or bulk defects, which could be caused by processes such as etching, cutting, drilling, or metal deposition.

TSMC reported on test interposers which consisted of 100 um diameter TSV drilled in 360 um thick glass substrates on 200 – 500 um pitch. The test structures had 1,521 I/O in area array on a 40 x40 mm substrate.

They found that glass fracture strength decreases with decreasing TSV pitch. Higher via density leads to less cross section area and lower strength is observed. Data scatter is reportedly  due to structural defect s inherent in the glass after processing. They found that coating the glass on both sides with a “thin film material” (which appears to be PI) resulted in marginal improvements (10-20%) in glass fracture strength.
 ANSYS modeling was employed to simulate the material deformation for stress and strain analysis when the package is simulated under temperature excursion. A flip chip BGA with BT substrate was modeled for comparison purposes. Solder material, die thickness, glass size, glass thickness, via diameter, via pitch, PI coating thickness and CTE of glass were all examined as variables. When replacing the BT laminate with glass ( CTE of 8..3 ppm) the deformation of the package increases from 0.15 to 0.27 mm due to the larger CTE mismatch between substrate and PCB. Due to reduced CTE mismatch between die and glass, the maximum stress is reduced by approximately 38% when compared to the organic substrate. The most significant factor appears to be die thickness. Thick Si die introduce higher stress on glass substrate, owing to its increased rigidity which restricts the glass and/or die from deforming to relieve the stress. The CTE of the glass is also important since higher CTE glass induces higher stress to the die. They found that a medium CTE (ca. 8.3 ppm) glass is better for lower die stress.
The substrate serves as an interposer between low CTE Si die and high CTE PCB. Glass with higher CTE reduces BGA balls stress but is harmful to the Si die and vise versa. Overall, from the TSMC simulations, the medium CTE glass substrate at around 8.3 ppm is demonstrated as the optimal choice for the package structure. Some of the other factors, such as glass thickness, via diameter and PI thickness do not seem to play a significant role to affect the stress of the die, BGA ball or glass.
A Georgia Tech PRC consortium is also looking at glass as an interposer candidate . The glass substrates (either borosilicate [CTE = 3.8 ppm]or “high CTE” [8.5 ppm] glass) are 180 um thick with 15 um thick polymeric coatings on top and bottom similar to the TSMC construction. The 30 um TSV are either filled or conformal. Panel sizes are currently 150 mm.

The conformal TSV exhibited similar electrical performance as the filled TSV but are expected to show better thermo-mechanical reliability behavior. Stresses in the polymer layers are higher for thicker layers as expected.
Electrical properties of the glass interposer were extracted from measured and simulated data on ring resonators [dielectric constant ~ 4.8 and loss tangent ~ 0.002 up to 19.4 GHz. Low insertion loss of less than 0.15 dB at 9GHz was measured for the TPVs in the thin glass interposer.
For all the latest in 3D IC and advanced packaging stay linked to Insights From the Leading Edgeâ??¦

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.