Insights From Leading Edge

IFTLE 56 Electromigration at the 2011 ECTC

[apologies for the formatting issues in IFTLE 55. With the move of SST to the "new platform" issues appeared when loading and editing IFTLE. Hopefully those issues are now resolved, and will never be seen again !]

We continue with our look at the major themes presented at this years ECTC Conference. This week we will look at presentations concerning Electromigration (EM).

Electromigration continues to be a topic of intense study. Several papers have reached the conclusion that copper pillar bumps are more EM resistant that normal UBM/ bump structures. Many groups are also concluding that the smaller micro bumps are also more resistant to EM.

ASE has released data from their studies on the effect of EM on RDL traces in wafer-level whip-scale packages. The first RDL structure was sputtered Ti/Al/Ti (0.2um/1.5um/0.2um) combined with a sputtered UBM: Al/Ni(V)/Cu (0.4um /0.325um /0.8um). The second RDL structure consisted of Ti/Cu/Cu (0.1um /0.2um /4, 6, or 7.5um electroplated Cu) combined with Ti/Cu/Cu UBM (0.1um /0.2um /8um electroplated Cu).

Based on Weibull characteristic lifetime plots derived from their data, ASE indicates that the maximum allowable electric currents for 100,000 h (11.4 years) continuous operation without electromigration damage for Ti/Al/Ti and Ti/Cu/Cu RDL with 25um wide RDL traces. The results indicate that Ti/Cu/Cu RDL performs better than Ti/Al/Ti RDL at low operating temperatures while features relatively shorter lifetime at high operating temperatures.

In a similar study on their eWLB package, Infineon finds that the most critical spots susceptible to EM voiding at high current loads turned out to be the terminations of RDLs with transition to the chip pad or the solder ball, respectively. The critical electron flow at the RDL/chip pad interface is the downstream direction since the current densities in the thin aluminum line are much higher compared to those in the thicker Cu RDL. The voiding occurs in the aluminum pad underneath the RDL via followed by liner punch-through. The interface between SAC solder ball and RDL shows a distinct bimodal failure behavior of which the root cause could not be identified. The upstream stress direction turned out to be the critical electron flow direction. The voiding is driven by copper migration and occurs at the very transition between RDL feeding line and solder ball, which is the location of the highest current density, defined Cu/Cu3Sn IMC boundaries and pre-existing Kirkendall voids. A significant boost in lifetime can be achieved by changing the ball pad construction (e.g. thick Cu UBM) or by means of layout optimization (RDL via size, RDL shape).

Amkor fabricated a special test vehicle to get a direct comparison of Cu Pillar EM with that of various solder bump compositions.  For solder bumps a TiW(1000A)/Cu(1500A)/Ni(2um) UBM stack was used. For Cu pillars, 55um of Cu was plated up on sputtered TiW/Cu. The Cu pillars were then plated with 20 and 40um SnAg solder to form solder caps. More than 8000 hours of testing on flip chip solder bump and Cu Pillar, revealed that Cu Pillars have the best reliability amongst the four bump metallurgies ( vs high Pb ,eutectic SnPb and SnAg ). 5 combinations of current and temperature were used to estimate the current carrying capacity of Cu-SnAg-Cu μ-bumps of 25um diameter. The Cu-SnAg-Cu micro bump structure was tested for 5500+ hours without any failures.

The EM results for the tested structures is shown below. The data shows lower EM performance for high Pb bumps compared to other bump compositions. High Pb bumps usually considered resistant to electromigration. Published data shows high Pb bump to be better performing than eutectic SnPb bumps. In this Amkor study, the failure analysis showed that the failures occurred on the substrate side with cracks occurring between the Cu-Sn intermetallics and substrate Cu pad. This study used a Cu SOP substrate finish and TiW/Cu/Ni UBM whereas previous data was based on ENIG finish on the substrate and Ti/Ni(V)/Cu UBM. The surface finish turned out to be the main reason for lower EM performance.

Cu pillar height was varied from 5 to 50um and current density distribution was determined under the pillar. Current crowding is highest with 5um thick pillar with maximum current density on the left side of bump (the side current flows in from). As the pillar height was increased, the current crowding ratio continued to reduce until the pillar height of 35um. A further increase in pillar height, however, started to increase the current crowding ratio slightly. Since lower pillar height is preferred for reducing stresses, Amkor concludes that a 35um pillar height might be optimum for both EM and mechanical reliability.

IMEC reported on their studies to compare standard NiAu/SAC  (SAC=SnAgCu) solder bumps with Cu pillar bumps in terms of their electromigration behavior. Both bump configurations were flip chipped onto package substrates with a thick Cu finish. The Cu pillar bumps, which are soldered with a thin SnAg cap do not show any significant electromigration damage and do not fail within reasonable testing times and test conditions. IMEC concludes that the rapid formation of a full intermetallic phase is believed to be the main course of the outstanding electromigration performance of the Cu pillar bumps. Standard solder bumps with Ni/Au UBM show a constant failure mechanism of micro-structural degradation through void formation at the interface of the solder and the intermetallics. This occurs for all test conditions used (150-170°C and 300-500 mA).

TSMC in two separate studies first compared the EM performance of C4 and micro bumps and then examined the EM effects of micro bumps in a 3DIC package.

1Ã??3 sq mm silicon test chips were populated with the 75-95um diameter SnAg solder bumps which are then mounted on a 12Ã??12 sq mm organic substrate. Surface finishes of both Cu SOP and ENEPIG were studied. For the micro bump EM samples, both  2Ã??3 sq mm and 3Ã??4 sq mm Si on Si stacked packages were used.

The resistance profiles of the stressed C4 bumps are distinctively different from those of the micro bumps. The early failure commonly observed in the C4 joint is not observed in the micro bump joint. The steady resistance increase in the micro bumps is dominated by IMC formation, which has much higher resistivity than that of Sn [The electrical resistance of Cu-Sn IMC is about 1.5 times more than that of pure Sn, 2.5 times more than that of pure Ni, and 10 times more than that of pure Cu.] There is no obvious void formation from EM stressing even though it has been stressed for a prolonged time with up to 6 times the current density of the C4 bumps.

TSMC concludes, however "this does not imply that the micro bump joints are immortal for EM. The failure can still occur by Cu consumption when disproportional amount of solder volume and UBM thickness is selected."

In their second paper EM effects of micro bumps in 3DIC package configurations were examined. Two structures were designed and fabricated: (1) joining of Sn-capped Cu post to ENEPIG (electroless-nickel-electroless-palladium-immersion-gold) UBM pad on silicon substrate and (2) joining of top Cu post to bottom Cu post that forms a symmetrical joint structure (shown below).

Resistance changes compared to a C4 bump are shown below.

The resistance shift profiles for both the post-on-post and the post-on-ENEPIG schemes are found to have rapid increase in the beginning and then steadily increment for the long run. TSMC correlates this to the solder wetting on Cu that allows for rapid Cu-Sn IMC formation upon EM stressing, and results in Cu continuing to diffuse for the long stressing period. The resistance change is controlled by the contact area of Cu-Sn interface. Since the solder wetting on Cu enlarges the Cu-Sn contact area, rapid IMC formation occurs. They conclude that "it is very crucial for precise control on the Ni fabricating process as Cu diffusion barrier between Cu and solder to limit the contact of Cu and Sn."

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