Insights From Leading Edge

Monthly Archives: December 2011

IFTLE 81: GIT @ GIT, Part 2

Continuing our coverage of the 2011 Global Interposer Conference at Georgia Tech:


Jerome Baron — Yole Développment

Baron reviewed the status of interposer applications, markets, players and costs. Several of the following speakers would tout the potential of glass as an interposer substrate material due to its perceived lower cost position, outstanding Rf performance, and its ability to be fabricated in large format. Baron compared and contrasted glass and silicon based interposers in the chart below. Henry Utsunomiya, president of Interconnect Technologies Inc., later predicted that glass interposers would be used for FC — CPU and GPU starting in 2013.

Glass producers in the audience such as Corning Glass and Asahi Glass indicated that they were actively pursuing glass interposer technology as part of the GaTech consortium program. Christian Nopper, R&D director of ST Micro-Tours, indicated that glass substrates are already being used for their Rf IPADS technology [Integrated Passive and Active Devices].

Yole concluded that panel size processing will be mandatory for 2.5D interposers to be broadly adopted in the packaging landscape.


Rao Tummala — GaTech

Rao Tummala, founding director of the GIT Packaging Research Center, laid out the case for the GIT Interposer consortium. They are studying both silicon and glass interposers and view their low-cost large-panel size solutions as eventual replacements for the BGA packages currently supporting the interposer and chips. Their low-cost silicon solution is linked to the use of polysilicon vs. crystalline Si wafers.

In his presentation on the electrical issues of interposers, GIT’s Madhaven Swaminathan pointed out that glass has lower insertion loss and a higher level of insulation than CMOS grade silicon, but glass has return path discontinuities so the insertion loss can be much higher than silicon. Looking at eye diagrams for glass and silicon, they actually concluded that silicon is the best.

Swaminathan concludes:

Si interposer
- Insertion loss is higher, but there are workarounds;
- Crosstalk can be a killer;
- Better thermal performance spreads the heat and reduces cross talk;
- Better power delivery

Glass interposer
- Insertion loss is low;
- Crosstalk is low;
- Localized heating is a problem;
- Power delivery could be challenging

Nanhoom Kim of Xilinx pointed out that there are several physical limitations imposed on the interposer due to cost, manufacturability, and reliability.

Kim also showed that when it comes to electrical performance, thicker oxide, shorter TSV, and smaller diameter are better.

Choon Lee, head of corporate technology for Amkor, reminded us that all DRAM is not equal. 4Gb DRAM DIMM for servers costs ~$250 whereas 4Gb DRAM for a PC is ~$20 — quite a difference. It’s clear why stacked memory is first headed for server applications!

Kai Zoschchke from Fraunhofer IZM provided this convenient plot of TSV resistance vs. aspect ratio:

For all the latest on 3DIC and advanced packaging stay linked to IFTLE……….

Last week to enter the IFTLE contest! See IFTLE #78 for details.

Next week: Update on 3D activities at the 2011 IEEE IEDM.

IFTLE 80: GIT @ GIT

The inaugural Global Interposer Technology Workshop (GIT) was recently held on the campus of GIT (Georgia Institute of Technology). While we usually report on conferences based on numbers of attendees and presentations, Karen May, GaTech coordinator of the conference, had a much more interesting measuring stick — reporting that the 138 attendees consumed 106 gallons of coffee, 83 pounds of pasta, and 12 dozen ice cream sandwiches. Over the next few blogs I will try to update you on what was presented and what was said. Several of the presenters (it will be obvious which ones) did not want their slides released, so in those instances I will be going from my handwritten notes.

While every conference even remotely linked to microelectronics feels pressure to have at least one session dealing with 3D integration, this workshop was started, and appears to be unique, in that it’s focus is solely on 2.5D i.e. interposers.

Row 2 (L-R): Swaminathan (GIT), Nopper (ST Micro), Sukumaran (GIT), Franzon (NC State), Huemoeller (Amkor), Matthias (EVG), Salmon (Semi), Kumbhat (GIT), Dunne (TI) ; Row 1 (L-R): Kitaoka (AGC), Ramalingam (Xilinx), Garrou (Assist Chair), Tummala (Chair), Dunne (TI)


Suresh Ramalingam — Xilinx

Certainly the highlight of the conference was Xilinx due to their highly publicized announcements on their Virtex 7 2000T FPGA, which uses a 21mm x 26 mm TSV interposer, which they have been sampling since September, and will have in full production in 2012. For details on the previous Xilinx announcements see [IFTLE 73, "Xilinx shows 2.5D Virtex 7 at IMAPS 2011" and IFTLE 23, "Xilinx 28nm multidie FPGA..."]. TSMC is fabricating the chip and the interposer, Amkor is bumping the chip and assembling the FPGA slices on the interposer, and Ibiden is fabricating the package substrate. Ramalingam emphasized that the interposer solution was necessary (vs. full 3D stacking) to insure proper thermal performance.

Increasing demand for FPGA capacity is reportedly coming from:

- Wired communications
- Image and video processing
- ASIC prototyping, emulation and replacement

All applications are constrained by the devices overall power budget and thermal concerns.

Full reliability qualifications are almost complete.

Future products are expected to be heterogeneous combinations such as the FPGA slices + SERDES chips shown below.

Doug Yu — TSMC

If the highlight was Xilinx, then the headline was TSMC, which concerning 3D and 2.5D has been very careful about what they say and how they are saying it — thus the comments made by Yu at this meeting drew great attention. Yu, Sr Director of Integrated Interconnects and Packaging at TSMC had some significant comments on 2.5D interposer supply chain developments. While there have been many recent proposals for how module fabrication tasks would be divided between foundries, IDMs, OSATs, and possible 3rd-party interposer suppliers, Yu proposed that for now, the interposers should be built completely by one party to define clear ownership and an efficient route to cost and yield improvements. Yu proposes that the foundries which can leverage their Cu processing capability, offer no customer competition (vs. IDMs), and have the design support capabilities would be the natural source for interposers. Furthermore, at several points during the two-day meeting, Yu reiterated that this is TSMC’s plan. However, you should also know that rumors in the audience indicate that TSMC is currently only engaging selected 1st-tier customers with their interposer technology, which should be no surprise. When asked when TSMC would be releasing their 2.5D ground rules, Yu indicated that TSMC does not release their ground rules for any of their processes except to their partner/customers.

While everyone knows that TSMC is engaged with Xilinx on bringing their FPGA product to commercialization, it was of great interest to see Yu commenting that they were also working on mixed-chip solutions (like the memory + logic depicted below ) using interposers with 10um x 100um TSV).


Bryan Black — AMD

Byran Black, CTO of AMD, indicated that AMD is taking a "very broad view of TSV and stacking" and that the industry "will stagnate if we don’t get 3D." While Black claims that AMD has been involved in 3D for more than five years, he added that they are "intentionally not talking about what we’re doing."

Most of us remember Black from his days at Intel. In the early 2000′s he was already publishing seminal 3D papers including "3D Processing Technology and Its Impact on iA32 Microprocessors" [Proc. IEEE Int. Conf. on Computer Design, pages 316-318, 2004]

IFTLE should note that a similar "stealth" approach was taken by Micron until its recent announcements concerning its memory cube technology — see IFTLE 74, "HMC — TheMemory Cube consortium."

The audience certainly took notice when Black stated that the "Southbridge" was probably the last AMD chip that would be impacted by scaling. He envisions that in the future chip companies will be focusing process node development on specific application functionalities. He contends this will reduce mask layers and run time and increase yield, while improving performance and reducing power requirements, area, and cost for each individual functionality. These separately fabricated functionalities would then be combined vertically and/or horizontally on an interposer to form the final circuit function.


Paul Franzon — NC State

Paul Franzon, Professor of EE at NC State and long time 3D practitioner, compared the capabilities of SoC vs. 2.5D vs. 3D, agreeing that thermal performance was the outstanding feature of 2.5D as shown below. He reiterated, as many others have, that performance is often limited by memory capacity and bandwidth.

Franzon detailed the concept of "dark silicon" where most of the chip must be in "off mode" at any given time to meet predetermined power budgets. Low-power 2.5 and 3D solutions are expected to alleviate this situation.

Franzon also concluded that stacking processor on memory would allow the processor temperature to be better controlled by attachment to the capping heat sink, but would not offer enough temperature differential to the memory underneath the processor which is in intimate contact. This differential is much better when using an interposer. [See a similar discussion by LSI in IFTLE 77, "MEPTEC 2.5, 3D and beyond."]

We’ll finish up GIT @ GIT next week and then cover IEEE IEDM and RTI ASIP — plenty of important 3D news is coming your way in the next few weeks!

Also don’t forget to enter our IFTLE contest — see IFTLE 78 for details!

For all the latest in 3DIC and advanced packaging stay linked to IFTLE……….

IFTLE 79: Deca Technologies: Is there data to back the hype? Intel picks Franzon group to design 3D IC microprocessors

When I first started writing PFTLE and now IFTLE, I never thought I would be using Bill Maher to make a point in these technology-based blogs, since he and I are as diametrically opposed as two people can get when it comes to most political positions. But, as they say, "never say never." For those of you not familiar with him, Maher is what is known in the US as a TV celebrity, which means that he has done absolutely nothing other than express his opinions. Anyway, one segment of his show that I sometimes do agree with is called "New Rules" where he shows you something being done in everyday life that makes no sense and then proposes a new rule to fix the situation.

One of my long-time peeves is the announcement of some new "breakthrough technological advance" that does not tell me what they intend on doing or how they are intending to do it. So I am proposing an IFTLE "NEW RULE": If you’re not going to tell me how you are going to do it (for whatever reason), please contain the hype.

Recent headlines concerning a startup beginning operation included: "Disruptive Approach & IP Will Revolutionize Electronic Interconnect;" "Charting a new course for the future of electronic systems, Deca has launched a breakthrough approach to creating advanced electronic interconnect solutions;" and "We can take products from design to manufacturing in minutes rather than days." While others were content to copy these headlines and pass them on to you without question, IFTLE expects significant technical backup data to justify such statements — and thus we give our "Where’s the Beef" "award" [see IFTLE 3: Finding the beef and addressing 3DIC"] to the WLP startup Deca Technologies.

Going to their Web page for further information provides little help. The tab "Find out about Deca technologies" leads to this statement: "Deca’s vision of how technology and processes can be improved addresses many of the key challenges associated with advanced packaging technology, driven by a single goal of providing breakthrough products and services. Deca delivers tangible benefits through excellence in innovation, responsiveness, and production performance, resulting in: – Rapid new product introduction, – Industry leading cycle time, – Optimized ROI." Hummmmm…where’s the beef?

The site’s "How are we changing the game" tab leads to this: "The Deca ethos strives for exponential improvements across the board through a philosophy called ’10x thinking. Through Deca, traditional wafer fab batch-based processes are giving way to a novel high speed approach. Put simply, our ’10x thinking’ ethos delivers flexible technology that saves money, reduces cycle time, and expedites the introduction of new products to market." Double-hummmm…

So what do we know for sure?

1. Deca is entering the WLP market. That would have been news in the mid 1990′s, but this is now a maturing, although admittedly still-growing industry segment.

2. Deca believes that by using "non traditional equipment" they can lower the pricing on these products. Of course, with no further explaination of what that "nontraditional equipment" is or its unique use.

3. Deca is convinced that their turnaround time will be significantly less that that currently offered. I read that as ASE, Amkor and the other OSATs. IFTLE contends that one should not brag about this until they have developed a track record for doing it.

4. IFTLE likes factual, low-hype announcements with deep technical backup. But as Dennis Miller (another US TV celebrity) says "That’s just my opinion; I could be wrong."

IFTLE wishes Deca nothing but good fortune and looks forward to reporting on what their technology is and how it is progressing in the future, when that information is eventually made public. Until then: A little less hype and a little more information, please.

$1.5M Intel grant to NC State to design low-power processors

A $1.5 million grant from the Intel Corp. will be used by Paul Franzon, lead researcher and Professor of EE and Computer Engineering at NC State University, to develop a 3D CPU with 15% to 25% better energy utilization. In addition to Franzon, the research team includes Eric Rotenberg and Rhett Davis of NC State, and Krishnendu Chakrabarty PhD. of Duke University.

One problem the participants plan to address is "how to reconcile chips that are designed and manufactured in different places to different specifications so that they can work together in three dimensions. [...] We will also address questions concerning heat dissipation." Franzon added that the goal is "at least a 15% improvement in performance per unit of power, through architectural and circuit advances."

They plan to have a prototype developed by 2014, and will also be addressing "test and yield" challenges — such as how manufacturers can test individual CPU components to ensure they are functional.

PFTLE/IFTLE Contest still underway

The contest involving naming key players in 3DIC and advanced packaging that have been discussed in the last several years by PFTLE/IFTLE is still ongoing and will be open to your guesses till December 31st.

See IFTLE 78 for rules and regulations and remember to send your guesses to pgarrou/contractor@rti.org if you want to win the MRS 3DIC book prize. Good luck to all of you!

IFTLE 78 Beginning 5 Years of PFTLE / IFTLE

As I said a few weeks ago, we have now entered Year 5 of Perspectives from the Leading Edge (PFTLE [link], in the now deceased Semiconductor International) plus Insights from the Leading Edge (IFTLE) that you find here every week in Solid State Technology. Both of these are due to the trust that Pete Singer, editor-in-chief, showed in me five years ago.

When I started many said it would be impossible to get enough fresh material for a weekly technical blog in 3DIC and advanced packaging. I think we have proved the naysayers wrong! I have tried to fill these blogs with the data, because we are scientists and we want to see the data. I have not made an exact count, but I would bet that there have been more than 1000 figures that have come to you in the more than 200 blogs as we enter Year 5.

I said IFTLE 78 would be something special — and I am a man of my word. First, I will review two of the most entertaining stories of the year, stories that hopefully made you laugh and will yet again. Then we will have a contest: the winner of the contest will win a copy of MRS volume 970: "Enabling Technologies for 3D Integration" edited by Bower, Garrou, Ramm and Takahashi, still in shrink wrap (photo at left). The winner will be determined by whomever can identify the largest number of people (name and current affiliation) that you have seen previously on the pages of PFTLE/IFTLE.

This is a take-home quiz so you can go back to the old blogs and check — but do it quickly! The winner will be determined as whomever sends in their email response the soonest, based on arrival date and time, at the following email address: pgarrou/contractor@rti.org. The contest officially ends on Dec. 31st, 2011. Only responses to that email will count — responses sent to my other email accounts will be disqualified. Employees of Pennwell, Microelectronics Consultants of NC, TechSearch International, Yole Développment, or Research Triangle Institute are disqualified (but can send in their guesses if they want to). The winner will be announced in early January 2012 along with a picture and short bio. Good luck to everyone!

Now for the two most entertaining stories of 2011…

The second most entertaining story can be found in IFTLE 47, "IBM 3D Cooling, TSMC Pkging, UMC 3D Equipment, the CIS Mkt Grows." This past spring at the Hanover Fair Germany, IBM CEO Sam Palmisano presented German Chancellor Merkel with a prototype of the IBM liquid cooling 3D chip stacking project developed at IBM Research-Zurich (see below). In front of the assembled audience and press, Merkel asked Palmisano: "Did you take this from Intel?" Quick on his feet, CEO Palmisano replied, "No, ours are better."

The Number One most entertaining story was reported in IFTLE 62 "Whats in a Name?" An EE Times article reporting on information released by the Taiwan External Trade Council quoted an "anonymous source" saying that "TSMC’s projected delivery of 3-D chips matches that of Intel, the world’s biggest chip maker". Only problem is that TSMC was talking about stacked 3D chips and Intel was talking about trigate transistors (i.e., finFETs). Nothing in the story made much sense since they were trying to compare apples to oranges — as many of the subsequent commenters pointed out.

Responses to this story by the EE Times readers were harsh:

- "TSMC is referring to 3D interconnect structures using through silicon vias. This has been in existence for quite some time, at least in R&D. What intel has built is a 3d transistor. There is a lot of difference between the two. Kindly refrain from misleading people. This is wrong information. Please correct…"
- "FINFET and TSV 3D are two completely different technologies. The report is confusion and misleading by comparing these 2 technologies…"
- "I agree that this article is terribly misleading and really doesn’t make a lot of sense as it mixes apples with oranges. I don’t think the author is technically very well informed on this subject…"
- " It’s a BS article – trying to make a connection to Intel Tri Gate is nonesense and misleading…"
- "Dumb article. As others have said, Tri-Gate transistor technology is a totally different thing than TSV interconnect technology…"
- "Beating Intel to 3D" by comparing TriGate to TSV is nonsensical…"
- "Is eetimes becoming a tabloid? I am wondering about the credentials of the article writer!"
- "I agree, what a pathetic article. I’m not an EE or even close to one, but even I know exactly how wrong and stupid this article is…"

WOW. We should note that EE Times offered an apology and correction shortly thereafter.

So, time for the contest… Below you will find the faces of 49 people whose stories have filled the pages of PFTLE/IFTLE over the years. Send in your guesses as to who they are and where they are employed — and you could win the prize! Good luck everyone, and thanks for your continued readership!

For all the latest in 3DIC and advanced packaging stay linked to IFTLE……….