Insights From Leading Edge

Yearly Archives: 2012

IFTLE 128: RTI 3D ASIP Part 1; Lester the Lightbulb update

Every year since 2005 the 3DIC season as ended with the Research Triangle Institute-sponsored Architectures for Semiconductor Integration and Packaging Conference (which I coined ASIP several years ago as I became tired of typing out the whole phrase). This conference — with its totally invited agenda — gives us a good chance to look back at what has happened during the year.

This year the preconference symposium (which has turned into course-like updates of the most recent technological advances) consisted of myself, Erik Jan Marinissen covering test, and Minsuk Suh of Hynix looking at the key challenges for wide IO applications.

The keynote session consisted of Xilinx, Micron, Cadence, GlobalFoundries, and Ericsson giving us a look at 2.5/3D progress from their perspectives.
Keynote speakers (l to r): Vinod Kariat (Cadence), Tom Pawlowski (Micron), Carl Engbloom (Ericsson), Dave McCann (GlobalFoundries) and Liam Madden (Xilinx)
Micron
Micron chief technologist Tom Pawlowski discussed revolutionary trends in memory technology and the role of 3D. He noted that "node scaling is becoming more difficult bot for logic and memory…we are getting close to the end of the CMOS S curve…the future will be dominated by technologies that offer the lowest energy consumption, i.e. picojules/bit." While there are significant aspect ratio and materials challenges for 3-D NAND (vertical transistor tech not 3D stacking), NAND is in the process of transitioning to "3D in fab" technology since it relaxes lithography requirements
Most practitioners feel that DRAM technology will be replaced. Opinions range from "mid-2015" to "by end of 2019." New technologies that may be used include:



Pawlowski indicates that the Micron HMC 3D stacking technology [see IFTLE 74, "The Micron Memory cube Consortium" and IFTLE 95, "...Further Details on the Micron HMC..."] has in fact rearchitected memory and equalizes signal transit time in the x, y, and z directions.

Micron offered the following memory stacking roadmap:

Tezzaron

Longtime RTI 3D ASIP attendee Bob Patti has had a quite eventful year at memory startup Tezzaron. Late this year they announced thepurchase of the old Sematech facility in Austin (which was owned by failing SVTC) and the licensing of the Ziptronix direct bonding technologies ZiBondâ??¢ and DBI®.

The Austin facility will now be known as Novati technology which Patti referred to as "a production-style fab that can also do development." It gives Tezzaron the control of production capacity which is something they have yearned for, for many years.
Concerning the Ziptronix license Patti commented that "no one technology can do it all…this gives us superior performance in die to wafer." 

Patti reiterated several times that he would be an open platform and is working with e-silicon to get this to customers. Promising to become part of the "domestic supply chain" Patti now has a 300mm, ISO 9000, trusted fab which can build in 65 nm CMOS and has 6-7 interposer programs already underway.
Tezzarons Bob Patti meets with (L) Kathy Cook and CEO Dan Donnabedian (Ziptronix) and (R) Matt Macray (RTI organizer) and Arif Rahman (Altera)
Lester the Lightbulb update
An engineer from the northeast who chooses not to reveal his name (political hacks now abound in the DOE and you certainly do not want to be called a non-believer!) sent an e-mail earlier in the month after he stumbled onto the IFTLE Lester articles. Here is his true story.
"…a couple of years ago I decided to put four LED PAR38 luminaires into my kitchen ceiling recessed cans. It took a couple of months for my wife to stop complaining about the harshness, but we eventually settled in and even got used to the half second startup time. Sadly, two of the luminaires failed within 18 months. Sylvania requires the original cash register receipt and UPC symbol, and most of us aren’t in the habit of saving such documentation on light bulbs. I’ve since rekindled my relationship with Lester."
Hmmmmm… methinks there are a lot more stories like this out there in the naked city [1950s US crime show humor].
By the way, several of these Lester articles have been picked up and retweeted and republished in the LED literature. Guess I won’t be invited to give the plenary lecture at any LED conferences, but that’s OK because I’m telling you the truth which is in short supply in some parts of the scientific community which have aligned with the politicos.

In my one-bulb, nonscientific test which we started in Aug 2011 [see IFTLE 63, "BiddingAdieu to Lester Lightbulb" ], recall the CFL burned out in less than a year [see IFTLE 109, "...Lester's cousin CFL dies prematurely..."] but the LED and Lester are still both burning as of the end of 2012.  Lester has now exceeded his 1000 hr expected lifetime. BRAVO LESTER ! Lester sent along this message from San Quentin where he still remains on death row but is running out of appeals.


"When I replaced the candle many years ago there was a reason for that and I think I bettered mankind. The dudes trying to extinct me now are doing so with lies because they are greedy bureaucrats who are on the take. CFL and LED are not the cheapest solutions for your lighting needs and reduction of the country’s energy consumption would be better done in other ways"

"If you don’t exterminate me I promise to be obedient (just flip the switch and I’ll come running); honest (you’ll never find me trying to bribe you to buy me or lying about my qualifications); thrifty (hey, what else can you buy now a days for a quarter?, not my competitors, that’s for sure!); brave (I’m trying to keep my chin up as those evil lying Washington lobbyists are accusing me of ruining our country); and clean (when I do finally pass away simply put me in the garbage can and I won’t poison your babies if I happen to break on your floor)."

Thanks, Lester, for all you have done for all of us….
For all the latest in 3DIC and Advanced Packaging stay linked to IFTLE…….

IFTLE 127: Christmas wishes and thin wafer processing

First things first:

In a recent Yole webcast, Eric Mournier took a market look at thin wafer bonding and processing.

Wafer thinning is required in a number of high growth microelectronic areas.

Thin (< 100μm) and even ultra-thin semiconductor wafers (< 40μm) are in demand for:

– Reduced package thickness
– Better heat dissipation / thermal management
– Increased TSV density

This brings up issues since the thinned wafers are more vulnerable to stress and the dies can warp and break.

Yole sees the following wafer thinning roadmap:

By 2017 memory will dominate the thinned wafer application space:

The major players will be the expected memory "Big 3" of Samsung, Hynix, and Micron:

They see greater than 10M wafers going through temporary bonding in 2017, which would be approximately 8% of total thinned wafers. The power and 3DIC markets will drive temporary bonding on carrier.

This will result in a temporary bonder / debonder market of $250M in 2017.

For all the latest in 3DIC and advanced packaging in 2013, stay linked to IFTLE………….

IFTLE 126: 2012 GaTech Interposer Conference, part 2

Continuing our look at the 2nd annual GaTech 2.5D Interposer Conference (for part one, see IFTLE 125: 2012 GaTech Interposer Conference, part I):

Ahmer Syed of Amkor took a look at micro bump electromigration issues. Issues inherent to electromigration have been around a long time [see IFTLE 56, "Electromigration at the 2011 ECTC"]. It is known that current densities on 10K A/cm2 will induce EM within a few hours.

When we look at 2.5/3D we have radically changed the dimensions involved as shown below.

There is a 20�? increase in interconnect density from BGA to μbump and a 10�? reduction in pitch and ball diameter. Yet for the μbumps shown below they saw no failures even after 16K hrs of operation.

They conclude that:

- For WLCSP and BGA joints, they see Cu consumption and failure around the circumference

- For μbumps, they see copper conversion and IMC formation either during assembly or during current/temp stressing, but they see very long life

- While current carrying capacity for BGA and FC joints are in the expected range, μbumps can carry much higher current than theoretically predicted.

- Cu pillar bump interconnects provides the highest current carrying capability.

Nagesh Vordharalli of Altera quoted an IMEC study which shows that the sweet spot for maximum bandwidth will come from interposers with RDL lines/spaces ~3μm. Nagesh feels that silicon based interposers need to be in the 1-2 cents/ mm range to compete with future high density laminate technology.

Professor Joungho Kim of KAIST shared his assessment of Si vs. glass interposer electrical performance. Imajo developed comparative data for double sided interposers with 10μm TGV/TSV on 40μm and 100μm pitch. TSV had oxide insulator thickness of 0.5μm. He proposes that interposer type will depend on IO count and bandwidth requirements as shown below.

Nobu Imajo of AGC reported on their ongoing activities to develop low-cost, high-density glass interposers. AGC is looking at EN-A1 glass because of its better CTE match to silicon. They use an e discharge process to form the TGV. They are currently working with 60um TGV on 100μm pitch. Below we see 300μm thick glass with 60μm TGV (entry) and 40μm (exit).

They are working on metallizing the TGV with copper. For thinner substrate structures, a glass carrier will be required.

Representing Yole Développement, I reported that 2.5D/3D interposer revenues in 2017 is expected to reach $1.37B, or 15% of the packaging substrate market value.

By 2017 Yole expects silicon interposers to exceed the revenue of their glass counterparts by at least 3.5:1. During the panel session, I indicated that to me it is highly unlikely that we will see OSATS buying flat panel display lines to produce glass interposers. It is much more likely that we will see current flat-panel producers become aware of the potential market for glass interposers and enter the market themselves.

For all the latest on 3D IC and advanced packaging stay linked to IFTLE……………

IFTLE 125: 2012 GaTech Interposer Conference, part I

Many of the world’s 3D elite meet the 3rd week of November at the 2nd annual GaTech 2.5D Interposer Conference which focused on the technology and performance of silicon and glass interposers. Chairs Tummala and Garrou assembled an expert panel of many of todays fabricators and users to deliver keynote addresses and answer attendee questions on where we are and where we are going. This meeting is sponsored by IEEE CPMT, IMAPS, iNEMI, and SEMI.

Expert panel from left: Jon Greenwood (GloalFoundries); Doug Yu (TSMC); Sesh Ramaswami(Applied materials); Joungho Kim (KAIST); Suresh Ramalingham (Xilinx); Sitaram Arkalgud (SEMATECH); Rao Tummala (GaTech); Subu Iyer (IBM); Matt Nowak (Qualcomm); Nagesh Vodharalli (Altera); Phil Garrou (Microelectronic Consultants of NC)

Sitaram Arkalgud outlined SEMATECH’s comprehensive 2.5/3D program which includes:

They see bonding going through an evolution which leads towards thermal compression copper-copper bonding on a less than 30μm pitch. Arkalgud reported that current copper-copper bonding occurs at 400°C with a throughput of 0.5 wafers/hour. The SEMATECH goal is to develop a process that can improve on both of those criteria.

They claim to have demonstrated a low time / temperature process (245°C / 5 min) on patterned wafers and have a tool concept proposed which could increase wafer throughput to 30 WPH.

The current SEMATECH roadmap for copper-copper bonding and thin wafer handing is shown below.

Jon Greenwood of GlobalFoundries shared their thoughts on "collaboration" and how important this is for complex infrastructures like 2.5D or 3D. Since both UMC and GlobalFoundries appear to be behind TSMC in the introduction of a qualified 2.5D process [see IFTLE 122: TSMC officially ready for 2.5D, Apple order impact on TSMC] and they have both publically supported a collaboration approach vs. the TSMC "one-stop shopping approach, presenting arguments for this approach was not unexpected. Greenwood indicated that 3D is being focused in Fab 8 in NY while 2.5D solutions are being focused in Fab 7 in Singapore. Process development was done in conjunction with IMEC in Belgium and Fraunhoffer ASSID in Dresden. They specifically call out the Big 4 OSATS as their assembly partners.

Matt Nowak of Qualcomm, long an advocate 3D technology, reported that Qualcomm has now built "thousands of parts" and does not see anything stopping high-volume manufacturing (HVM) except cost.

Qualcomm defines high density for 2.5/3D as: 5-10μm TSV, AR ~ 10:1; 1K-10K TSV / μbumps; 10′s μm bump pitch. They see the following categories evolving:

Nowak indicates that Qualcomm will require a price of ~$2 for a 200 mm2 high-density silicon interposer. The high-density aspect is out of the reach of those proposing low-cost "coarse" interposer fabrication and the pricing appears significantly out of reach for the pricing structure for dual damascene foundry-based fine interposers.

For all the latest on 3D IC and advanced packaging, stay linked to IFTLE………………

IFTLE 124 Status and the Future of eWLB; Will Deca lower the cost of FO-WLP ?

First and most importantly, in the US we just had our "Thanksgiving" holiday weekend. This means I was with granddaughters Hannah and Madeline in NYC for the Thanksgiving parade and then a long… long… long shopping time at the American Girl store. Here they are posed in front of American Girl. For those keeping track they are now 8 and 5.

Now back to the technology………… With the recent announcement by STATSChipPAC (SCP) that they are offering eWLB as a platform for 2.5D-3D packaging solutions [link] IFTLE thought that it was a good time for a review of the status and future of fan-out WLP (FO-WLP).

Nanium

In October, Nanium, one of the first semiconductor companies to build volume capacity for 300mm eWLB wafers in late 2010, announced that it has shipped its 200 millionth eWLB component for wireless communications and other applications.

Nanium announced that they had recently adapted eWLB technology for consumer MEMS, stacked die DRAM multichip packages for high-capacity memory applications, mixed-signal RF ASIC, and heterogeneous integration within System-in-Package (SiP).

Steffen Krohnert, Nanium’s director of technology, reports that "Intel usage of the eWLB packages is for wireless consumer products (modems, RF, SoC), mainly baseband and RF chips, and also for full low-cost mobile phone on SoC…we even see increasing volumes and higher number of products in eWLB coming from Intel Mobile Communications (IMC), which is now part of the new Intel Mobile and Communications Group (MCG) and we see interest in other parts of MCG such as the Connectivity Group (MWG)."

Krohnert also reports Nanium has " ~ 20 R&D projects with semiconductor companies to implement eWLB for their products." Examples for new eWLB markets and applications include "stacked memory, heterogeneous integration for medical and security SiP, mixed-signal ASIC, RF and high-power dissipation applications, ASIC + MEMS SiP, PMU, optoelectronics/ fiber optics SiP, mm-wave/ 60GHz radar products… long-term we plan also to introduce eWLB in automotive applications, e.g. MEMS + ASIC SiP."

Yole Developpment

Yole Developpment has recently updated its "FOWLP & Embedded Die Packages" report [link]. The FOWLP market is said to have reached the $100M market last year with Nanium and SCP representing 81% of this production mainly driven by Intel Mobile’s volume demand on eWLB production.

Lionel Cadix, market & technology analyst at Yole Développement, indicates that "This young industry will need to wait until 2015-2016 to reach $200M, as the demand will shift from IDMs to leading fab-less wireless IC players, such as Qualcomm, Broadcom, Mediatek, etc… and will be supported by the solid infrastructure of ‘top 4′ major assembly houses."

He continues with the observation that "low reliability on large package body size and lack of flexibility in the IC to package co-design process are the two main factors limiting the wide adoption of FOWLP technology in the wireless IC market. Indeed, FOWLP technology imposes a specific redesign of the chip for efficient integration into the package: both Infineon and ST Ericsson (who already have products on the market) spent almost 18 month to redesign their baseband and RF-Transceiver SoCs in order to place the pads at optimized locations and match with a single RDL, 0.5mm board pitch eWLB package design. FOWLP is a restrictive package technology for most of the world’s IC designers to adopt efficiently, especially fabless chip companies. This is why only big semiconductor IDM companies having IC-to-package co-design environments well established in-house can drive and support the initial growth of this new wafer-level-packaging platform at its early stages."

Cadix reports that OSAT players ADL (TW), Amkor and NEPES (SG) are reading production and TSMC and SPIL are expected to have production ready in 2013-2014.

Infineon (GE) was the first company to commercialize its own eWLB packaging technology in an LGE cell-phone in early 2009 (see cross section below) Infineon’s chip is a wireless baseband SOC with multiple integrated functions (GPS, FM radio, BT…). The same eWLB product has also been in production in Nokia handsets since 2010.

Infineon wireless baseband SoC

LGE (wireless baseband), Samsung (baseband modem), and Nokia ( baseband modem and RF transceiver) have used eWLB in their cell phone products.

Deca Technologies

Chris Scanlan, VP of product management for Deca Technologies, recently gave a presentation entitled "Adaptive Patterning for Panelized Packaging" which described the company’s M-Series platform of embedded die (FOWLP) packaging.

Scanlan reported that their new process avoids the current pick-and-place positional accuracy and mold compound shrinkage issues inherent to current FOWLP processes. Die position accuracy of < 10μm and rotational accuracy of < 0.1° are typically required which in turn requires slow pick-and-place speed.

In Deca’s "Adaptive Patterning" process, die with copped studs (think copper pillar bump) are placed onto a carrier and molded into a 300mm wafer. Wafers are then removed from the carrier and planarized to reveal the copper studs. The wafer is imaged and the position of each die is imported into a proprietary software.

Connections are then made between the standard pad positions and the actual positions of the placed die. Deca has not disclosed the lithography process, but we do know that there are no traditional glass masks involved — which certainly helps explain their claimed fast turn around time. Industry conjecture is that some sort of laser processing is involved.

Customers have not been identified, although parent Cypress is probably one of them. Deca says it is "sampling to a limited set of customers with broader availability planned for 2013."

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE……………………

IFTLE 123: Intel’s Bohr on 3DIC; Samsung DDR4 roadmap; Amazon to buy TI mobile chip unit? ; Communication will soon be king

Insight into Intel and 3DIC

For those of you that haven’t read Ed Sperling’s recent interview with Intel’s CTO Mark Bohr in Semi Manuf and Design, it contains some interesting comments on the 3D area [link]:

SMD: Where do stacked die fit into your roadmap?

Bohr: 3D stacked die have advantages, but only for certain market segments. You have to be very clear about what problem and what market segment you are trying to serve.

For a small handheld application where a small footprint and form factor are key and power levels are low, it probably makes good sense to use 3D stacking. For desktop, laptop and server applications where form factor isn’t as valuable and power levels are higher, 3D stacking has some problems that make it not an ideal solution.

And his thoughts on interconnect…

SMD: Is the interconnect [on chip] becoming more problematic?
Bohr: If you talk to a designer 10 years ago you would have heard the same thing. Maybe now they’re saying, ‘This time we’re really serious.’

SMD: How about new interconnect technology?
Bohr: It’s hard to replace copper and low-k other than by making lower k. But at least in the low-power cell phone market, stacking chips does help to minimize some of the interconnect issues, particularly between the logic and the memory chips.

SMD: You’re referring to through-silicon vias?
Bohr: Yes.

SMD: So if Intel is planning to get into that market, the company is experimenting with that technology right now?
Bohr: Yes, and we’ve been public about exploring TSV and 3D technology for a couple years. Although there are some challenging technology aspects, the real issue is cost. Doing TSVs and stacking chips — especially these custom Wide I/O chips — is expensive. So this might be a better engineering solution in terms of density, performance and power, but will the market bear the added cost? Not all markets will bear the higher cost.

Intel to use DDR4 with TSV starting in 2014?

Despite these comments, IFTLE would be remiss if we didn’t point out that rumors continue to swirl that Intel will use 3D stacked DDR4 memory in their Haswell-EX platform for enterprise computing [link].

Since Haswell will feature microprocessors with 12-14 cores, it will benefit from lower memory power consumption, higher memory bandwidth, and the memory capacity that DDR3 simply cannot provide. DRAM makers will make high-capacity DDR4 chips using through-silicon-via (TSV) technology that will allow to increase capacity of memory chips at a very fast rate. For servers, special switches will be introduced to avoid one module/one channel limitation.

Samsung DDR4

Indeed, Samsung demonstrated its next-generation DDR4 chips and memory modules at the Intel Developer Forum. Samsung showed a 300mm wafer of DDR4 die processed using 30 nm technology, insinuating that it could start production of DDR4 anytime the infrastructure became ready. Samsung plans to take DDR4 module speed for 2014 servers [like Haswell-EX?] to 2.666 GHz. Eventually, Samsung and Intel intend to boost the effective clock-speeds of DDR4 server memory modules to rather whopping 3.20GHz.

It is reported that in DDR4 memory sub-systems every memory channel will support only one memory module. To enable the highest-possible memory capacities, DRAM makers will use TSV stacking to make high-capacity DDR4 chips. Special switches will be used in server modules to avoid this module/one channel limitation.

Amazon in talks to buy TI’s mobile chip business?

Last month Texas Instruments announced plans to shift its focus away from its mobile processor business (~ $650M sales) and target broader markets such as industrial clients in the car industry, and Wall Street has speculated it could be sold.

Now, according to a report from Israeli newspaper Calcalist, Amazon is said to be in "advanced negotiations" to acquire this business from TI. This would be a step towards vertical integration for production of its Kindle tablets and could indicate an interest in entering the smartphones business. TI’s processors are used in Amazon’s Kindle Fire tablet. Amazon CEO Bezos reportedly touted TI’s industry strength at their new tablets recent launch. Speculation has existed for more than a year that Amazon could sell its own smartphone but Bezos has not addressed those rumors. The 1.0 GHz dual-core Texas Instruments 4430 OMAP application processor runs the Kindle Fire [link].

Reuters reports that Amazon declined to comment on the report. TI said it does not comment on rumors but said in an email to Reuters: "The smartphone market has become a less attractive long-term opportunity for TI … and we are re-profiling our investment accordingly."

If this sounds strange, why is it that different than Microsoft with its traditional business model of licensing operating systems to PC manufacturers, who will this month will launch the "Surface tablet," which it designed itself?

Communications to surpass computers as leading application for ICs

Our friends at IC Insights in their study, "IC market drivers 2013: A study of emerging and major end-use applications fueling demand for integrated circuits," forecasts communications applications to pass computer applications as the leading end-use for ICs starting in 2014 and lasting through at least 2016. The IC communications market is forecast to grow 9.2% in 2012 to $90.0 billion from $82.4 billion in 2011, and increase 11.7% to $100.5 billion in 2013, breaking the $100-billion level for the first time. The total communications IC market is forecast to reach $114.4 billion in 2014, 4.6% more than the $109.4 billion computer IC market. From 2011 to 2016, the communications IC market is forecast to grow by a cumulative annual growth rate (CAGR) of 14.1%, reaching $159.5 billion at the end of the forecast period. The communications segment accounted for 31.2% of worldwide IC sales in 2011 and the computer end-use segment 41.7%. By 2016, these two segments will flip-flop, with communications forecast to represent 42.2% of the total IC market, compared to 34.0% for the computer segment.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…………

IFTLE 122: TSMC officially ready for 2.5D, Apple order impact on TSMC

An event that many of us have been waiting for, for a long time finally happened a few weeks ago. At the recent TSMC Open Innovation Platform Ecosystem Forum on October 16th, TSMC announced the foundry reference flow supporting CoWoS (Chip-on-Wafer-on-Substrate) within their open innovation platform (OIP) [link].

The validated CoWoS reference flow enables "multi-die integration to support high bandwidth, low power and achieve fast time–to-market for 3D IC designs." The CoWoS flow allows designers to use existing, mainstream tools from leading EDA vendors. It reportedly allows "a smooth transition to 3D IC with minimal changes in existing methodologies." It includes the management of placement and routing of bumps, pads, interconnections, and C4 bumps; innovative combo-bump structure; accurate extraction and signal integrity analysis of high-speed interconnects between dies; thermal analysis from chip to package to system; and an integrated 3D testing methodology for die-level and stacking-level tests.

TSMC also announced that they have taped out the foundry segment’s first CoWoS test vehicle using JEDEC Wide I/O mobile DRAM interface [link]. This test vehicle demonstrates the integration of a logic SoC chip and DRAM into a single module using the Wide I/O interface. Along with Wide I/O mobile DRAM, the integrated chips provide optimized system performance and a smaller form factor with significantly improved die-to-die connectivity bandwidth. Ecosystem partners included: Wide I/O DRAM from Hynix; Wide I/O mobile DRAM IP from Cadence Design Systems; and EDA tools from Cadence and Mentor Graphics.

EDA systems in place

It seems like only yesterday there were no EDA tools for 2.5/3DIC [ see PFTLE 23, IMEC arrives in Hsinchu and other 3D IC News]. IFTLE is happy to announce that that is no longer the case with several EDA companies including Cadence, Mentor, Synopsys and Ansys were announced by TSMC as partners for their CoWoS reference flow.


[Cliff Hou, VP R&D TSMC, and CP Hsu, VP R&D Cadence]

Cadence announced that TSMC has validated Cadence 3D-IC technology for its CoWoS reference flow with the development of a CoWoS test vehicle that includes an SoC with Cadence Wide I/O memory controller and PHY IP [link]. This is the foundry segment’s first silicon-validated reference flow enabling multiple die integration.

The validated technologies in the 3D-IC solution include: the Cadence Encounter RTL-to-signoff and Virtuoso custom/analog platforms; the Cadence system-in-package products, and recently acquired Sigrity power-aware chip/package/board signal integrity solution that helps

engineers overcome die-stacking and silicon carriers’ challenges from planning through implementation, test, analysis and verification. TSMC’s unique CoWoS combo bump cells, which simplify bump assignment, are now supported automatically in the Cadence Encounter Digital Implementation (EDI) System, QRC Extraction, and Cadence Physical Verification System. The CoWoS Reference Flow is supported with a CoWoS design kit and silicon validation results from a TSMC test vehicle.

Mentor Graphics announced IC physical design, verification, thermal analysis and test design tools that have been selected for TSMC’s new CoWoS (Chip on Wafer on Substrate) Reference Flow [link].

The Olympus-SoC product supports "probe pad routing including micro bump and C4 bump routing, routing between combo bumps, and combo bump stream out in DEF and GDS formats. Inter-die design rule checks (DRC) and layout versus schematic (LVS) checks are performed during layout construction to help ensure rapid signoff."

The Pyxis IC Station custom layout product "provides redistribution layer (RDL) routing and ground plane generation with the ability to do 45 degree angle routes to vias, and specific enhancements for the TSMC flow include improvements to the bump file import process".

The Calibre 3DSTACK sign-off tool verifies physical offset, rotation, and scaling at the die interfaces. It can also trace connectivity and extract interface parasitics to enable multi-die performance simulation. Calibre and FloTHERM 3D computational fluid dynamics software have been integrated to model temperature variation across the CoWoS design.

The Tessent solution enables 3D IC testing. The Tessent test tool " addresses 3D IC multi-die integration challenges including management of placement and routing of micro-bumps, probe-pads, through-silicon-vias (TSVs), and C4 bumps, accurate extraction and signal integrity analysis of high-speed interconnects between dies, thermal analysis from chip to package to system, and integrated 3D testing methodology for die-level and stacking-level tests".

Key features for 3D IC include:

  • Pre-bond testing of TSVs and IOs using contactless wrap;
  • Retargeting of embedded compression scan patterns and built-in self-test (BIST) created at the die level to any die in the stack using DFT access infrastructure;
  • Test generation for shorts or opens between logic die;
  • Test generation for shorts or opens between DRAM and logic die using the memory die’s JEDEC interface;
  • Enhanced memory BIST for thorough testing of vendor independent stacked DRAM die.

Synopsys announced a 3D-IC design solution that is also included in TSMC’s CoWoS reference flow [link]. In support of CoWoS Synopsys has released enhanced versions of its Galaxy Implementation Platform tools for physical implementation, parasitic extraction, physical verification and timing analysis.

TSMC has validated Synopsys’ implementation, analysis and signoff tools, including:

Physical implementation: IC Compiler multi-die physical implementation with support for placement, assignment and routing of microbump, thru-silicon via (TSV), probe-pad and C4; combo bump cells allowing simplified and flexible bump assignment; microbump alignment checks; redistribution layer (RDL) and signal routing, and power mesh creation on CoWoS interconnection layers.

Analysis and signoff: (a) Hercules layout vs. schematic (LVS) connectivity checking between stacked die; (b) StarRC Ultra parasitic extraction support for TSV, microbump, RDL and signal routing metal for CoWoS design interconnection and (c) PrimeTime timing analysis of multi-die systems.

ANSYS and subsidiary Apache announced that their simulation tools were selected for TSMC’s CoWoS reference flow to meet power, noise and reliability requirements and manage thermal run-away, stress and thermal-induced electromigration on 3D-IC structures. RedHawk, Totem, Chip Thermal Model (CTM) , Sentinel-TI ANSYS SIwave and ANSYS Icepak, provide a complete system-level thermal analysis with consideration for chip behavior across CoWoS designs.

TSMC will take over Apple orders from Samsung by 2014

During SEMICON Taiwan last month Gartner predicts TSMC is likely take over all of Apple’s processor contracts (from Samsung) by 2014. Gartner predicted Samsung’s LSI unit will manufacture 700,000 wafers for Apple processors in 2012 with a value of ~ $2.1 B.

Gartner predicts that if Samsung loses all its contracts to TSMC, TSMC would see revenue increases >10% (Gartner estimates TSMC’s 2012 revenues at $16 B).

For all the latest on 3DIC and advanced packaging stay linked to IFTLE……………………………….

(Note the hotel change! Redwood City not Burlingame)

IFTLE 121 SEMICON Taiwan 2012 part 2

Continuing with our look at 2.5/3D and packaging activities at SEMICON Taiwan.

EVG

Markus Wimplinger of EVG addressed "Thin die stacking for wide IO memory-on-logic." EVG points out that adhesive thickness for temporary bonding is dependent on the topography being covered, as shown below.

When examining solder reflow bonding and thermo-compression bonding, EVG concludes that reflow soldering does not work for fine pitch bonding (less than 40μm; see Amkor disc above):

- Dies are very thin. Stress causes dies to bend. No mechanical contact between interconnects
- Fine pitch required reduction of solder volume. Reduced solder volume results in lower tolerance for height variations and / or bow and warp of chips

Thermocompression bonding which is becoming standard for fine pitch interconnect has a typical cycle time of 4-16 sec.

SEMI

Dan Tracy, director of industry research and statistics for SEMI, presented their 2012 "Fab equipment and materials market update." Of interest in the TSV materials forecast (obtained from Linx Consulting) is their claim that "bonding adhesives" accounts for >50% of the current (2012) ~$25MM market and still has >45% of the projected 2016 $450MM market. The "cleaning" number of ~22% in 2016 is also remarkable. Since IFTLE has found no temp adhesive materials suppliers willing to quote a current or future price for the materials, we find these numbers, as the Japanese would say, "very difficult."

Cadence

Jiayuan Fang of Cadence presented "Exploring silicon interposers through system co-design and co-analysis to maximize performance." He offered the following interposer system design flow:

Yole

In the market trends forum, Baron of Yole Développment addressed "3DIC and TSV interconnects: 2012 business update." Their latest TSV chip wafer forecast is shown below:

Yole is forecasting that the IBM’s Power 8 chip and the Intel Haswell and the Sony PS4 will all be based on 2.5D interposer technology. [see IFTLE 88: Apple TSV Interposer rumors; Betting the Ranch ; TSV for Sony PS-4; Top Chip Fabricators in Last 25 Years] The Sony GPU + memory device may look something like the Global Foundries demonstrator shown below.

Yole projects the silicon/glass interposer substrate market reaching $1B by around 2016, at which point it will have penetrated ~10% of the IC substrate packaging market.

Both Micron and Samsung have announced that they will be ready to release wide IO 3D stacked memory in 2013.

Corning Glass

In the Executive Summit Forum, Peter Bocko, CTO of Corning Glass, gave a presentation entitled "Glass: Enabling next-generation, higher-performance solutions." While glass has currently been shown to function as a carrier during the thinning operation, the case is made that glass can be used as the interposer substrate. The ability to produce roll-to-roll or on large panels is the driving motivation.

Quoting reports from the GaTech consortium, Corning points to glass interposers showing less warp during chip assembly, faster signal propagation, and significantly reduced signal loss. In fact, they found a 10Ã?? lower signal loss in glass for a 6Ã?? longer interconnect. Such a 60Ã?? lower leakage improves power efficiency.

Significant advancements are being made in fabricating and filling TGV (through-glass vias) as can be seen in the figure below.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE………………………….

IFTLE 120: SEMICON Taiwan 2012, part 1

This year’s 3DIC forum at SEMICON Taiwan was entitled “3D-IC Supply Chain Readiness.” With most industry leaders who are currently involved in 3D development believing that the realization of 3D-IC technology into high-volume manufacturing is not a question of “if” but rather only a question of “when,” this year’s forum was focused on industrial readiness and infrastructure maturity. Representatives from manufacturing supply chains, ranging from EDA to foundry/OSAT, shared their views through presentations and an open panel.

Dr. Ho Ming Tong (left) , general manager and chief R&D officer of ASE and Dr Mike Ma, VP of Corporate R&D for Siliconware, chaired the Symposium and delivered opening remarks. Speakers included Amkor, Aptina, Cadence, EVG, LSI, Teradyne, Tohoku-MicroTec, UMC, and Xilinx

UMC

Kurt Huang gave a presentation entitled “Foundry TSV Enablement For 2.5D/3D Chip Stacking” — making it clear that they will be ready to compete with TSMC in the foundry interposer and 3D stacking business.

Recall UMC has been looking at the 3DIC area for quite a while, having been in a developmental relationship with Elpida and PTI [see IFTLE 8, “3DInfrastructure, Announcements and Rumors”] since 2010.

UMC envisions several work flow models (shown below) and concludes that each OSAT / foundry will have their own capabilities and preferences.

UMC indicates that their foundry design rules for interposer fabrication are ready to go, with product level packaging & testing and reliability assessment scheduled for completion in 4Q 2012.

Typical 3D TSVs are 6 �? 50 and for interposer are 10 �? 100 um. KOZ have been determined to be 5μm for 28nm HKMG core device with TSV pitch: JESD229 50/40μm.

Amkor

Min Yoo of Amkor Taiwan gave a presentation entitled “3D IC Technology: The OSAT Perspective.” Amkor sees: (1) partitioning logic blocks into higher-yielding sub-blocks as is being done by Xilinx and others in the FPGA arena — this results in lower cost 28nm products as well as chips that are less sensitive to 28nm processing issues; and (2) repartitioning SoC devices into separate functions which allows for using the latest node (i.e. 28nm) only where it is required. The latter has been discussed previously by Bryan Black of AMD [see IFTLE 80, “GIT@GIT”].

Also of interest is the Amkor roadmap showing Application processors + DDR for smartphones and tablets being scheduled for 2014.

Amkor, as expected, is in favor of a supply chain where the TSV are fabricated by the fab / foundry and then shipped to the OSAT for subsequent processing.

They highlight the fact that they are involved with the current Xilinx FPGA product . Their copper pillar μbump technology is commercial at 40μm, demonstrated at 30μm, and in development at 20μm.

We will continue with more presentations from SEMICON Taiwan next week.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE……………………………………

IFTLE 119 ICECool Puts 3D Thermal Issues back in Focus

Keeping it Cool

Back in 2008 we addressed 3D cooling activities [see PFTLE 43, "Keeping it cool in the dog days of summer"] looking a the activities at IBM Zurich, GaTech, and CALCE (U Md) as the groups especially active in this area.

Since then we have looked further at the liquid cooling activities of Bakir at GaTech [see IFTLE 83, "Orange County IEEE CPMT 3DIC Workshop"] and Brunschwiler at IBM Zurich [see "IBM to use water cooling for future 3D IC processors"] and the fact that one of the drivers for 2.5D is that it offers better thermal performance that current 3D stack solutions [ see IFTLE 97, "DATE in Dresden, Synopsys 3D EDA solution"]. For the most part, though, IFTLE has taken the position that thermal would not be the roadblock for 3DIC and that initial products would be ones where the thermal solution was not driving the technology.

Now that we are quickly approaching full commercial production of a number of products, it’s probably a good time to focus more on proposed thermal solutions for the future. To update yourself on where things stand, I suggest Herman Oprins’ article "Modeling and experimental characterization of hot spot dissipation in 3D stacks." He concludes that thermal management issues in these 3D stacks are one of the main challenges for 3D integration since the use of polymer adhesives with low thermal conductivity, the presence of interconnection structures, back end of line (BEOL), redistribution layers (RDL), and through-Si vias (TSVs) increases the complexity of the conductive heat transfer paths in a 3D stack.

Oprins concludes that hot spot power dissipation results in significantly higher temperatures in 3D stacked chips compared to the same power dissipation in single 2D chips. This temperature increase is mainly due to the reduced thermal spreading in the thinned dies on the one hand, and to the use of adhesives with low thermal conductivity for the vertical integration of the chips on the other hand. To limit the temperature increase in 3D-ICs, "too thin chips should be avoided" because the thinner the silicon substrate, the higher the thermal spreading resistance is in the case of hot spots. Simulations show that a minimum die thickness of 50μm is required to deal with the local hot spots on the thermal test chip they used.

Their study on the impact of TSVs on the temperature profile in the test chips showed that the presence of the die-die connections, such as Cu or CuSn microbumps or direct Cu-Cu bonds, is more important than the presence of the TSVs itself. The Cu TSVs with high thermal conductivity (390 W/mK) are inserted in the Si, which is conductive (150 W/mK at room temperature and120 W/mK at the operating temperature). Conductivity values for the underfill materials are typically 0.2 W/mK for unfilled underfills and 0.3-0.4 W/mK for filled underfills, depending on the amount and type of filler particles. The difference in thermal conductivity between the metallic bonds and the adhesive material is thus two orders of magnitude. As a result, "well placed dummy microbumps, rather than dummy TSVs, can be used to increase the effective thermal conductivity and to reduce the temperature increase in a 3D stack."

Many of you are aware of DARPA’s BAA 12-50 ICECool an effort of CALCE’s Avi Bar-Cohen within DARPA’s Microsystems Technology Office (MTO). ICECool Fundamentals is the initial thrust and first BAA of DARPA’s ICECool program.

The specific goal of ICECool Fundamentals is to demonstrate chip-level heat removal in excess of 1 kW/cm2 heat flux and 1 kW/cm3 heat density with thermal control of local sub mm hot spots with heat flux exceeding 5 kW/cm2, while maintaining these components in their usually accepted temperature range by judicious combination of intra- and/or interchip microfluidic cooling and on-chip thermal interconnects. ICECool Fundamentals is, thus, the first step toward achieving the system performance goals of the ICECool program and will develop the fundamental building blocks of intrachip and interchip evaporative microfluidic cooling.

ICECool Fundamentals will, over an anticipated 24–36 months, develop and demonstrate the microfabrication techniques needed to implement thermal interconnects and evaporative microfluidics in multiply-microchanneled semiconductor chips, and study, model, and correlate intrachip heat diffusion and the thermofluidic characteristics of evaporative flows in microchannel flow loops within individual chips and/or in the microgaps between chips in 3D stacks — without compromising the combination of intra- and/or interchip microfluidic cooling and on-chip thermal interconnects in one of several possible semiconductor wafers.

They offer the following schematic as an interchip approach:

and required responses to deliver on the following metrics.

There will be several winners to this first "fundamentals" BAA and hopefully we will be seeing the next generation 3DIC thermal stacking technology evolve from the government-supported program. IFTLE will keep you informed as the winners are announced and their proposed thermal solutions become public.

For all the latest on 3DIC and advanced packaging stay linked to IFTLE………………………………..