For those of you paying attention, you will have noticed that IFTLE has been stuck on 107 for nearly a month.
Has all progress stopped in 3DIC ?…..NO
Has all progress stopped in Advanced packaging ?……NO
Are there no new industry rumors ?……NO
So whats up IFTLE where is our new information ???
It’s as simple as IT issues at the main SST server….boring ….but true.
Now that we are back up:
Lets catch up with technical highlights of the 2012 ECTC Conference.
Wafer Underfill processing (NCF)
Toray presented results of their study on suppressing wafer level underfill (WUF) material entrapment at copper pillar/Pad joints. The NCF was laminated on the wafer and then the surface was planarized by the bit cutting technique. Chips are then bonded to cu/Ni/Au pads.
(Click on any of the images below to enlarge them.)
When the top chip and lower chip are joined the temp must be raised slightly (sticking process) to get the NCF to flow together. This holds the two chips in place.
Factors Controlling NCF
Namics reported on the parameters controlling NCF performance. One of the main issues with NCF has been voiding. Namics reports that one of the causes of voids is captured air which is generated when an IC connects to NCF. This relates to the flow of resin. They could decrease the voids by optimizing the minimum melting viscosity. Another type of void comes from volatilization of gases may occur from organic materials in the structure such as the substrate. They found that the higher minimum melting viscosity is, the more effectively this type of voids can be controlled. They also optimized the minimum melting viscosity, curability and flux-ability for good interconnection. When the minimum melting viscosity is too high, the connection is poor. When cure speed is too high, solder melting is blocked. They attempted to optimize flux activity, and found that gelling time, minimum melting viscosity and oxidation-reduction power need to be controlled.
Hitachi Chemical (HC) also reported on their attempts to optimize their NCF products. HC reports that The major requirements for processability are (1) NCF can be laminated to the bumped wafer without air trapping around the bumps and dicing lines; (2) In the process of back grinding, the wafer laminated with NCF can be grinded back side (opposite side of NCF) to thinner wafer without damage such as wafer crack and delamination of NCF; (3) the alignment mark or dicing pattern on the wafer can be recognized through NCF; (4) the NCF-laminated wafer can be diced without damage such as chip crack and delamination of NCF.
Issues and solutions are listed in the table below:
Compression Molding Compounds for Fan out WLP and MUF
Hitachi Chemical (HC) reported on their studies on using solid molding compounds for fan out WLP and molded underfill (MUF) . Currently, liquid molding compounds are mainly used for eWLB as encapsulant. Liquid molding compound issues include cost, warpage and high die stand-off caused by molding shrinkage.
HC shows that solid molding compounds has better wafer warpage results that liquid wafer warpage. Package warpage was almost flat over the temperature range tested.
High filler content is necessary for such molding compounds. Lower temp curing is also useful to lower warpage due to reduction in thermal shrinkage. Post mold cure is 150C for 1 hr.
Using solid molding compounds for MUF, flip chips can be molded/underfilled at 130 C / 250 sec.
Koyanagi-san and co-workers at Tohoku Univ have looked at the sue of NCF and compression molding for 3D integration using self assembling technology. They examined chips with 20 um pitch Cu-SnAg microbumps with bump height ~ 6 um ( 3 um thick Cu and 3 um thick SnAg). The chips were self assembled face up on a carrier wafer. Then, the chips were transferred to the corresponding target wafer with microbump-to-microbump bonding through a NCF. The strength of temporary bonding was lower than the microbump bonding through the NCF, and thereby, the chips were removed from the carrier wafer and successfully transferred to the target wafer. After that, the target wafer having the chips bonded upside down on the wafer was packaged by a compression molding technique with a granular resin that covered all over the self-assembled chips to planarize the chip-on-wafer structure. Finally, the chips and the resin were simultaneously thinned from the backside of the chips.
For all the latest on 3DIC and advanced packaging (hopefully in a week or less) stay linked to IFTLE…………….