The Latest from TSMC
Ken Liu of Taiwan Economic News reports that TSMC is aggressively hiring for their 2.5/3D packaging and test unit and will have a team of over 400 specialists ready for this business area [link]. Reports are that they have hired experts away from ASE, Siliconware and Powertech to fill these vacancies.
In the past IFTLE has insinuated that TSMC was working with a half dozen primary customers in the 2.5D area. Liu now names them as Xilinx, AMD, Nvidia, Qualcomm, TI, Marvell and Altera Corp.
Reports in Taiwan are that TSMC lost the chance for making Apple A3 processors to Samsung because of its lack of the capability to package and test the chips. TSMC management reportedly now feels confident of securing Apple’s foundry contracts for next-generation processors. The A6 ??Per Steve Liebson here is a close up of the TSMC / Alterra 2.5D (which TSMC is now calling their chip-on-wafer-on-substrate CoWoS technology) test vehicle which we have previously described [ link]. It was evidently was on display at the Cadence booth at the recent design automation conference. TSMC describes the 2.5D circuit as being composed of 65 nm GPS, 45 nm DRAM and 28 nm SoC.
(Click on any of the images below to enlarge them.)
3DIC SEMI Standards
The Inspection and Metrology Task Force of the Semi 3D standards group, recently approved its first Standard ,SEMI 3D1, Terminology for Through Silicon Via Geometrical Metrology. SEMI 3D1 will provide a starting point for standardization of geometrical metrology for selected dimensions of through silicon vias (TSVs). Although different technologies can measure various geometrical parameters of an individual TSV, or of an array of TSVs, such as pitch, top diameter, top area, depth, taper (or sidewall angle), bottom area, and bottom diameter, it is currently difficult to compare results from the various measurement technologies as parameters are often described by similar names, but actually represent different aspects of the TSV geometry.
Other standards under development by the Inspection & Metrology Task Force include SEMI Draft Document 5270, Guide for Measuring Voids in Bonded Wafer Stacks, SEMI Draft Document 5409, Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks, SEMI Draft Document 5410, Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures, and SEMI Draft Document 5447, Terminology for Measured Geometrical Parameters of Through-Glass Vias (TGVs) in 3DS-IC Structures.
The Thin Wafer Handling Task Force is focused defining thin wafer handling requirements including physical interfaces used in 3D-IC manufacturing. Current standards for shipping are not well-suited for the reliable storage and transportation of thin wafers and dice on tape frames used in 3D-IC manufacturing. Wafer thicknesses of 30-200um will need significant changes to the current design criteria of current wafer transport and storage containers. SEMI Draft Document 5175 aims to address the robust handling and shipping of thin wafers, including changes in securing the wafers.
The Bonded Wafer Stacks Task Force is near completion of its SEMI Draft Document 5173, Guide for Describing Materials Properties and Test Methods for a 300 mm 3DS-IC Wafer Stack and SEMI Draft Document 5174, Specification for Identification and Marking for Bonded Wafer Stacks.
Current wafer standards do not adequately address the needs of wafers used in three-dimensional bonded wafer stacks for stacked integrated circuits. In each step of a 3D-IC process, the incoming material must be specified in terms of wafer dimension and materials present. Wafer thickness, edge bevel, notch, mass, bow/warp and diameters change when wafer stacks are bonded, debonded, and when wafers incorporated into stacks are thinned. Further, these parameters will change for a single wafer stack during process. This Document will provide the required properties of both silicon ("device") wafers and glass ("carrier") wafers to be used in 3D-IC applications. Templates for describing bonded wafer stacks and processed wafers to be used in the bonding flow would be provided as well.
The Middle-End Task Force is focused on the middle-end processes on wafers with or without TSVs, including post-final metal temporary bonding, wafer thinning, TSV formation and reveal, micro-bumping, redistributed line formation and carrier de-bond. The task force’s first two proposals are SEMI Draft Document 5473, Guide for Alignment Mark for 3DS-IC Process, and SEMI Draft Document 5474, Guide for CMP and Micro-bump Processes for Frontside TSV Integration.
Further details on the Semi standard efforts can be found here [link].
Sony Stacked Image Sensor
CMOS image sensors are used in a wide range of Sony products, including digital cameras, digital camcorders, DSLR cameras and Android based smartphones. Sony has focused on key traditional parameters such as increased pixel counts, improved resolution and higher speed. January 2012, Sony announced that it had successfully developed a 3D stacked CMOS image sensor complete with TSV. In place of the supporting substrate used in conventional back-illuminated CMOS image sensors, this image sensor stacks the back-illuminated pixels layer onto chips containing the circuit section for signal processing which facilitates greater functionality and compactness. The new structure is positioned to become the next generation of back-illuminated CMOS image sensors.
In the figure below Sony compares their new stacker CMOS image sensor to previous advancements such as Exmor (on chip column parallel A/D conversion) and Exmor R (backside illuminated). The size gains are obvious.
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