Dr. Ho Ming Tong (left) , general manager and chief R&D officer of ASE and Dr Mike Ma, VP of Corporate R&D for Siliconware, chaired the Symposium and delivered opening remarks. Speakers included Amkor, Aptina, Cadence, EVG, LSI, Teradyne, Tohoku-MicroTec, UMC, and Xilinx
Kurt Huang gave a presentation entitled “Foundry TSV Enablement For 2.5D/3D Chip Stacking” — making it clear that they will be ready to compete with TSMC in the foundry interposer and 3D stacking business.
Recall UMC has been looking at the 3DIC area for quite a while, having been in a developmental relationship with Elpida and PTI [see IFTLE 8, “3DInfrastructure, Announcements and Rumors”] since 2010.
UMC envisions several work flow models (shown below) and concludes that each OSAT / foundry will have their own capabilities and preferences.
UMC indicates that their foundry design rules for interposer fabrication are ready to go, with product level packaging & testing and reliability assessment scheduled for completion in 4Q 2012.
Typical 3D TSVs are 6 Ã?? 50 and for interposer are 10 Ã?? 100 um. KOZ have been determined to be 5Î¼m for 28nm HKMG core device with TSV pitch: JESD229 50/40Î¼m.
Min Yoo of Amkor Taiwan gave a presentation entitled “3D IC Technology: The OSAT Perspective.” Amkor sees: (1) partitioning logic blocks into higher-yielding sub-blocks as is being done by Xilinx and others in the FPGA arena — this results in lower cost 28nm products as well as chips that are less sensitive to 28nm processing issues; and (2) repartitioning SoC devices into separate functions which allows for using the latest node (i.e. 28nm) only where it is required. The latter has been discussed previously by Bryan Black of AMD [see IFTLE 80, “GIT@GIT”].
Also of interest is the Amkor roadmap showing Application processors + DDR for smartphones and tablets being scheduled for 2014.
Amkor, as expected, is in favor of a supply chain where the TSV are fabricated by the fab / foundry and then shipped to the OSAT for subsequent processing.
They highlight the fact that they are involved with the current Xilinx FPGA product . Their copper pillar Î¼bump technology is commercial at 40Î¼m, demonstrated at 30Î¼m, and in development at 20Î¼m.
We will continue with more presentations from SEMICON Taiwan next week.
For all the latest in 3DIC and advanced packaging stay linked to IFTLE……………………………………