Now back to the technology………… With the recent announcement by STATSChipPAC (SCP) that they are offering eWLB as a platform for 2.5D-3D packaging solutions [link] IFTLE thought that it was a good time for a review of the status and future of fan-out WLP (FO-WLP).
In October, Nanium, one of the first semiconductor companies to build volume capacity for 300mm eWLB wafers in late 2010, announced that it has shipped its 200 millionth eWLB component for wireless communications and other applications.
Nanium announced that they had recently adapted eWLB technology for consumer MEMS, stacked die DRAM multichip packages for high-capacity memory applications, mixed-signal RF ASIC, and heterogeneous integration within System-in-Package (SiP).
Steffen Krohnert, Nanium’s director of technology, reports that "Intel usage of the eWLB packages is for wireless consumer products (modems, RF, SoC), mainly baseband and RF chips, and also for full low-cost mobile phone on SoC…we even see increasing volumes and higher number of products in eWLB coming from Intel Mobile Communications (IMC), which is now part of the new Intel Mobile and Communications Group (MCG) and we see interest in other parts of MCG such as the Connectivity Group (MWG)."
Krohnert also reports Nanium has " ~ 20 R&D projects with semiconductor companies to implement eWLB for their products." Examples for new eWLB markets and applications include "stacked memory, heterogeneous integration for medical and security SiP, mixed-signal ASIC, RF and high-power dissipation applications, ASIC + MEMS SiP, PMU, optoelectronics/ fiber optics SiP, mm-wave/ 60GHz radar products… long-term we plan also to introduce eWLB in automotive applications, e.g. MEMS + ASIC SiP."
Yole Developpment has recently updated its "FOWLP & Embedded Die Packages" report [link]. The FOWLP market is said to have reached the $100M market last year with Nanium and SCP representing 81% of this production mainly driven by Intel Mobile’s volume demand on eWLB production.
Lionel Cadix, market & technology analyst at Yole Développement, indicates that "This young industry will need to wait until 2015-2016 to reach $200M, as the demand will shift from IDMs to leading fab-less wireless IC players, such as Qualcomm, Broadcom, Mediatek, etc… and will be supported by the solid infrastructure of ‘top 4′ major assembly houses."
He continues with the observation that "low reliability on large package body size and lack of flexibility in the IC to package co-design process are the two main factors limiting the wide adoption of FOWLP technology in the wireless IC market. Indeed, FOWLP technology imposes a specific redesign of the chip for efficient integration into the package: both Infineon and ST Ericsson (who already have products on the market) spent almost 18 month to redesign their baseband and RF-Transceiver SoCs in order to place the pads at optimized locations and match with a single RDL, 0.5mm board pitch eWLB package design. FOWLP is a restrictive package technology for most of the world’s IC designers to adopt efficiently, especially fabless chip companies. This is why only big semiconductor IDM companies having IC-to-package co-design environments well established in-house can drive and support the initial growth of this new wafer-level-packaging platform at its early stages."
Cadix reports that OSAT players ADL (TW), Amkor and NEPES (SG) are reading production and TSMC and SPIL are expected to have production ready in 2013-2014.
Infineon (GE) was the first company to commercialize its own eWLB packaging technology in an LGE cell-phone in early 2009 (see cross section below) Infineon’s chip is a wireless baseband SOC with multiple integrated functions (GPS, FM radio, BT…). The same eWLB product has also been in production in Nokia handsets since 2010.
LGE (wireless baseband), Samsung (baseband modem), and Nokia ( baseband modem and RF transceiver) have used eWLB in their cell phone products.
Chris Scanlan, VP of product management for Deca Technologies, recently gave a presentation entitled "Adaptive Patterning for Panelized Packaging" which described the company’s M-Series platform of embedded die (FOWLP) packaging.
Scanlan reported that their new process avoids the current pick-and-place positional accuracy and mold compound shrinkage issues inherent to current FOWLP processes. Die position accuracy of < 10Î¼m and rotational accuracy of < 0.1° are typically required which in turn requires slow pick-and-place speed.
In Deca’s "Adaptive Patterning" process, die with copped studs (think copper pillar bump) are placed onto a carrier and molded into a 300mm wafer. Wafers are then removed from the carrier and planarized to reveal the copper studs. The wafer is imaged and the position of each die is imported into a proprietary software.
Connections are then made between the standard pad positions and the actual positions of the placed die. Deca has not disclosed the lithography process, but we do know that there are no traditional glass masks involved — which certainly helps explain their claimed fast turn around time. Industry conjecture is that some sort of laser processing is involved.
Customers have not been identified, although parent Cypress is probably one of them. Deca says it is "sampling to a limited set of customers with broader availability planned for 2013."
For all the latest in 3DIC and advanced packaging, stay linked to IFTLE……………………