Part 2 in our look at the RTI ASIP Conference which occurred in Dec 2012.
Lionel Cadix of Yole updated 3DIC and 2.5D Interposer market trends and technological evolutions. He showed the following TSV wafer forecast by market segment.
As of 2011 the top 3 players in 3D TSV revenue were all CMOS image sensor fabricators. That is expected to change in the next two years as the memory suppliers come on line.
3D stacked DRAM and 3D Logic SOC applications are expected to be the biggest drivers for volume adoption of 3DIC technology in the next five years.
Riko Radojcic presented the following Qualcomm assessment of where things stand in 3DIC technology. This indicates that we are in the productization mode worrying about business models and yield ramps and not any technical issues.
In terms of design status he offered the following:
Paul Silvestri of Amkor shared their perspective on the readiness of 2.5/3D technology and manufacturing. Silvestri indicated that "3D memory delivery has been slowed down a bit" and that Amkor does not see interposers going into mobile phones simply because there is no room for them" (This is something Matt Nowak of Qualcomm has been saying for years).
Thinning and backside processing is pretty much ready to go with the only exception being bond/debond which still needs improvement.
– Fine Pitch Cu-Pillar technology is well established in high volume production
– Wafer thinning equipment and infrastructure is well established with excellent
thickness variation control at 2 micron
– Backside silicon etch equipment and infrastructure is well established with excellent
uniformity variation control at ca. 3%
– Backside passivation (SiN and TEOS) equipment and infrastructure are well
established with excellent thickness variation control at ca. 2 micron
– Backside passivation polish equipment and infrastructure is well established with
excellent thickness variation control at ca. 1 micron
– Backside bump Equipment and infrastructure is well established with high volume
capability in industry
– Wafer support equipment and infrastructure is well established with high volume capability in industry but the process is still in need of improvement
Back End of Line Processing
Testing of the memory stack is required prior to committing memory to package stack. The memory stack in this construction is the largest cost item.
The preferred sequence in most instances is interposer to substrate and then chips/memory stack to interposer because it follows the standard OSAT processing flow. In nearly all cases the foundry inserts the TSV (TSV middle) but then the wafers are finished either at the foundry (TSMC preferred) or at the OSATS (GlobalFoundries & UMC preferred).
Amkor’s take on interposers is as follows:
Stacked Memory Sources
Silvestri indicates that there are only two primary memory sources today. KGM is received on tape and reel, stacked memory in wide I/O format typically 2 die stacks, but some 4 die stacks.
Amkor projects the following financial benefits from 3DIC.
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