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IFTLE 142 GlobalFoundries 2.5 / 3D at 20nm; Intel Haswell GT3; UMC / SCP Prototype Details

GlobalFoundries

 A year ago [see IFTLE 102, "3.5D Interposers tosomeday replace PWBs” - TSMC; GF engaging with 3D customers; Intel predictsConsolidation"] GlobalFoundries (GF) CTO Bartlett announced the installation of TSV production tools for the company’s 20nm technology platform and announced that "the first full flow silicon with TSVs was expected to start running at Fab 8 (Saratoga NY) in Q3 2012 with mass production expected in 2014 and the 2.5D line ( their 65 nm Fab 7 line in Singapore) had  a similar time schedule as the 3D line in the United States."

Last week, GlobalFoundries announced its first functional 20nm silicon wafers with integrated through-silicon vias (TSVs). At its Fab 8 facility in N.Y., the silicon foundry vendor manufactured TSV test wafers using their 20nm-LPM process technology, and at Fab 7 in Singapore, the company demonstrated a 65nm 32mm x 26mm interposer test vehicle for 2.5D chips. Both 2.5D and 3D are set for a 20nm introduction, full qualification by next year and non-early adopter production in 2015.

They are using a 6 x 60 um vias middle, copper TSV  as shown in the figure below. Interposer size is limited by reticle size i.e. 25-30 mm.

Dave McCann, VP of packaging technology at GlobalFoundries, reports that GF is taping out a 3D design for an undisclosed customer and is working with two others on 2.5D. "2.5D is already here," he added. Several 2.5D test structures were shown that were collaborations with Amkor.
While foundries TSMC and Samsung [see IFTLE 133, "SEMI ISS 2013 Comments from Samsung, GF,Intel and others"] are both offering turnkey solutions,  GlobalFoundries and UMC are supporting a partnering ecosystem where they will handle the traditional front-end steps and the "via creation" process and then will hand off the traditional backend steps such as temporary bonding/debonding, grinding, assembly and test to traditional packaging houses such as ASE, Amkor SCP and SPIL.
A year ago, GF announced hopes of shipping 28 and 20nm 3D chip stacks in 2014. Now, GF states only the 20nm chips will be used in stacks and they may not ship in volume till 2015.

Intel Haswell GT3

This past fall [see IFTLE 123: Intel's Bohr on3DIC] IFTLE reported rumors that Intel would be using TSV stacked DDR4 memory in their Haswell-EX platform for enterprise computing.

Haswell is the codename for the successor to Ivy Bridge architecture. Intel is expected to release 22nm CPUs based on Haswell around June 2013 according to leaked roadmaps. Current rumors have it that the Haswell GT3 will be the introduction point for 2.5D stacking and interposers. Semiaccurate [link] reports that Intel codename "Crystalwell" is not L4 cache on package but rather is GPU memory on an interposer. They indicate that the GT3 variants of Haswell will have 64MB of on-package memory connected through an ultra-wide bus.

Reports were that Haswell needed lower memory power consumption, higher memory bandwidth, and memory capacity that DDR3 could not provide but wide IO TSV based memory stacks could. Based on recent reports from the Semi 3D summit where ST Ericsson’s Kimmich concluded that "although 3D TSV technology appears ready for mass production, wide IO technology is not yet a fit for mainstream smartphones. LPDDR3 and LPDDR4 will be used in this application due to better thermal performance and lower cost."  [see IFTLE 134 “SEMI 3D European Summit – Isthe Wide IO Driver Dead ?”]                                                                        

IFTLE must ask whether these Haswell "requirements" can be met with the newly described LPDDR3 and LPDDR4 solutions, which do not use TSV technology.
UMC / STATS  Update
A few months ago, IFTLE reported that foundry UMC and OSAT partner STATSChipPAC (SCP) had announced a jointly developed TSV-enabled 3D IC chip stack consisting of a Wide I/O memory test chip stacked upon a TSV-embedded 28nm processor test chip below).  This was developed under their open ecosystem collaboration using UMC’s foundry capability and STATS ChipPAC’s packaging capabilities. [See IFTLE 135, "UMC / SCP Memory on Logic"]
Several readers have reported that this structure (above) is from a TI OMAP 5 platform application processor and that the program with UMC and SCP was terminated when TI dropped out of the application processor market. (Thats probably why the xsect image was made available!)
For all the latest in 3DIC and advanced packaging, stay linked to IFTLE.


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  1. Pingback: IFTLE 161 Semicon Suss Workshop part 2: GF, Amkor, Nanium | Insights From Leading Edge

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