Insights From Leading Edge

IFTLE 147 IME Updates 2.5D; Qualcomm Updates 2.5 / 3DIC at ICEP

IME Updates Interposer Research

In the latest issue of Future Fab Int Singapores IME updates their 2.5D through-silicon interposer (TSI) technology development [link]

GQ Lo, deputy Director Director of Research, and his 3D group point out that "3D IC…is confronting bottlenecks, such as tools for designing optimal 3D systems and thermal solutions for 3D ICs" and that "2.5D through-silicon interposer (TSI) technology is gaining momentum, both in the foundry and the outsourced semiconductor assembly and test (OSAT) universe."

They state that interposer technology provides easier fabrication, alleviates 3D thermal bottlenecks and supports the fabrication of heterogeneous integration. They demonstrate the fabrication and characterization of a 2.67 x 4.3 cm2 interposer on a 300 mm processing line. Processor + memory integration is an ideal 2.5D application since "dies can be heterogeneous (e.g., logic and memory) and can belong to different technology nodes (e.g., 28nm for logic and 40nm for memory, or 130 nm for BiCMOS chips."

The TSV (12 µm x 100 µm ) were Bosch etched into a 300mm wafer. TEOS oxide was deposited to isolate the TSV from the silicon substrate; Ti / Cu sputtered as a barrier metal and copper seed. Copper was electroplated, and overburden removed by CMP after copper anneal. Three single-damascene processes were applied to form frontside M1, via and M2 on top of the TSV.

ZoneBOND technology was used for wafer temporary bonding and de-bonding. TSV wafer was back-ground to near TSV depth, the remaining silicon substrate was etched to expose the TSV from the wafer backside and low temp dielectric films deposited and CMP’ed. Back side barrier metal and Cu seed were sputtered on the back side dielectric, and the RDL was plated up, patterned and bumped.

The cross-section of TSV and FS metal is shown below.

The electrical performance (C-V and I-V curves) of the interposer was characterized for TSV capacitance (CTSV) and leakage current after top M2 metallization and before TSV reveal.

The leakage between four TSVs with connection pad to silicon substrate (measured TSV good dies after C-V characterization) is less than 1 pA for a voltage range 0-100 V, suggesting satisfactory isolation between the TSV and the silicon substrate.

The yield of the front side M1-TSV-BS RDL chain and front side M2-via-M1-TSV-BS RDL chain were 90 percent and 85 percent, respectively.

Resistance of the TSV and backside RDL (line/space 10/10 µm) are shown below:


Qualcomm at ICEP

At the recent ICEP (Int Conf on Electronic Packaging) in Osaka Japan, Qualcomm’s Umi Ray presented "Architecture Trends in Mobile Industry and Impact on Packaging and Integration," updating their smartphone activities "one device many functions." They supported the Gartner projection that 5 billion smartphones will be sold between 2012 and 2016.

Ray proposed that we would be seeing 2.5 / 3D in our phones soon and showed the following roadmap, although the time axis was left vague:
The first implementation target will be wide IO memory on logic and so far, they have seen "no technical show stoppers." As we have discussed in the past, pricing remains the key challenge.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.


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