Continuing with our coverage of the March IMAPS DPC.
In his keynote presentation on semiconductor packaging trends Devan Iyer of TI showed a great chart on package shrinkage through the years. We have moved from the 1.75mm SOIC to the picostar 2G at 0.075mm which they claim to be the thinnest package available for portable products and can be buried into PCB layers .
Iyer also listed the following packaging challenges for materials and assembly.
Dev Gupta of APSTL examined “Stacked package with improved bandwidth and power efficiency” . His conclusions are based on the assumption that 2.5/3D technology is still immature and high cost and not ready for adoption in consumer products like smart phones. He is a proponent of what he calls “super PoP” packages.
Gupta claims that the issues for Pop arise from increased power loss due to parasitics in the package and that this can be cured by inserting “signal conditioning chips “ (442)
Nanium announced that they were installing 30mm WL fan in technology (Spheron PBO technology from Flip Chip Int) to compliment their WL fan out technology already in place.
Corning discussed their 3D carrier glass substrates used in the wafer thinning process.
They supply glass carriers for the 3M temp bond / debond process. Their fusion glass process results in surfaces with RMS 0.3nm; Ra 0.2 nm and Z range 4.2nm which is better than lapped and polished glass.
200 & 300 mm wafers cut out of a sheet. 450 will not be a problem and panels are ready when the industry becomes ready to use them.
They are using alumino-silicate glass (SGW3) to match CTE od Si from 0 – 300 C. This CTE match keeps warpage very low. Corning pointed out that measuring TTV on these wafers is difficult and that reports in the literature of 1 um TTV are sometimes as far off as 5 um.
Recycling glass wafers depends on all process perameters, but in general they envision 15 recycles as doable.
For all the latest in 3DIC and advanced packaging stay linked to IFTLE………….