Insights From Leading Edge



IFTLE 159 Semicon Suss Wkshp part 1: Material Suppliers; IEEE 3DIC Program

Am I the only one who missed Semicon West?

I had a full week of workshops and 1-on-1 meetings set up for Semicon West, but due to the Korean crash, United canceled my Sunday flight and rebooks me for Tuesday night (I’m a million mile flier, so imagine the service the peons got!) then my replacement Delta flight was cancelled on Monday again with no seats on flights into SF, Oakland or San Jose till late Tuesday. I finally concluded some things are simply not meant to be.

The Suss technology forum that I helped set up and was set to moderate went on without me so I’d still like to cover some of the materials that were presented there.

Let’s look first at the material suppliers.

Lord

Le of Lord gave a presentation on their photo definable silica filled epoxy “solder brace” material which they propose to use as a final passivation in a standard WLP redistribution process.

We are shown data concluding that the “solder brace” shows better thermal cycling reliability (-40 to +125 C) and drop test results then an unidentified “PI” , but without clear understanding the identity of the PI and all the design dimensions involved (such as thickness of the screen printed epoxy vs the spun PI) it is hard to draw any substantial conclusions from the data.

Since screen printing is not a usual unit operation in a standard redistribution process this might be a barrier to acceptance for such a filled product.

Click to view full screen.

Click to view full screen.

Brewer Science

Smith of Brewer Science detailed the separation technologies available for their ZoneBond Process. The temporary adhesive ring of the ZoneBond process can be removed either by immersing the temp bonded wafer on a perforated carrier in a solvent bath as shown below:

Click to view full screen.

Click to view full screen.

Or,  by trimming the narrow bonded ring post fabrication to release the device wafer, where:

-          Debonding occurs at room temperature.

-          Separation occurs at the carrier-to-adhesive interface, not the adhesive-to-device interface.

-          Device is mounted in the film frame and is firmly supported on a vacuum chuck during debonding.

This allows higher-temperature-capable adhesives

-          Thermally stable in bonded pair to 240°-260°C (depends on processing parameters)

Click to view full screen.

Click to view full screen.

Dow Corning

Ho of Dow Corning presented their new silicone based bi-layer temporary bonding solution. Their Bond/Debond Process Flow is shown below.

- Spin-coat bi-layer (release and adhesive layer)

- Room temperature bonding / debonding

- post-bonding cure on hot plate

- no plasma or lasers necessary

- fast mechanical debonding

Click to view full screen.

Click to view full screen.

Dow Chemical

Gallagher of Dow Chemical detailed their photo and laser patternable plating resists and dielectrics for WLP and 3D TSV.

Their Novolac (positive) and Acrylate (negative) resists are capable of a brad thickness range.

Click to view full screen.

Click to view full screen.

Their Cyclotene (BCB) dielectrics are laser patternable and their Intervia (epoxy) dielectrics show excellent vertical sidewalls. They also highlighted BCB as a temporary bonding solution which shows high thermal stability during backside processing ( , 1% weight loss at 300 C per hr) and clean RT mechanical peel-off debonding.

Suss

Lutter, of Suss, compared the temporary bonding solutions that Suss supports focusing on the room temp mechanical debonding solutions.

Click to view full screen.

Click to view full screen.

The mechanical release at RT is described as follows:

Click to view full screen.

Click to view full screen.

Zonebond and several other solutions show excellent TTV (2-3um) after thinning to 50um.

Click to view full screen.

Click to view full screen.

Flex frame tape is a key to good debonding and cleaning . The principle of Suss debonding is shown below.

Click to view full screen.

Click to view full screen.

IEEE 3DIC

The IEEE’s premier 3DIC conference is on tap for the USA again this year. The conference will be held in San Francisco the first week of October. You can register here [link]

Let’s take a look at the program:

Click to view full screen.

Click to view full screen.

Wednesday, October 2nd  – Free Tutorials!

13.00 – 14.00 Tutorials: 2.5/3DIC Players, Products & Markets, Rozalia Beica – Yole Developpement

14.00 – 15.00 Tutorials: 3DIC – Prof. Mitsu Koyanagi, Tohoku University

15.00 – 16.00 Tutorials: Design for 3DIC, Prof. Paul Franzon – NCSU

16.00 – 17.00 Tutorials: TSV and Interposer Design for High Performance and Low Noise,  Kim- Kaist

17.00 – 18.00 Tutorials: Monolithic 3DIC, Zvi Orbach

Thursday, October 3rd

08.30 – 09.45: Keynote Speaker: Prof. M. Taklo, SINTEF, Title:” E Brains”

09.45 – 10.15: Invited Talk I “ 3DIC Activity at Tohoku “  Prof. Mitsu Koyanagi, Tohoku University

13.00 – 13.30: Invited Talk II – “A Perspective on Manufacturing 2.5/3D”  Robert Patti, Tezzaron

17.00 – 18.00: Panel Session “Progress and Outlook for 3D ICs and 2.5D Systems -

Moderator: Jan Vardaman, TechSearch

Friday, October 4th

08.30 – 09.00: Invited talk III “The DARPA ICECool Program”  Avi BarCohen, DARPA

Hope to see you all there.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE.

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