Insights From Leading Edge



IFTLE 174 DARPA ICECool Efforts for 3DIC Stack Cooling

At the IEEE 3DIC in SF in October, DARPA program manager Avi Bar Cohen presented the history of device cooling at DARPA and how it has evolved to the embedded cooling of 3D stacks.

It is well known that microprocessor frequency stopped increasing around 2005 when air cooling met its limits.

fig 1

Traditional cooling involves heat rejection to a remote fluid involving thermal conduction and spreading in substrates across multiple material interfaces as shown below.

fig 2

Such technology cannot:

- limit  the device “junction” temperature rise

- selectively target the thermally-critical devices

- extract heat efficiently from a 3D package or 3DIC stack

What is needed to take us to the next level is an embedded cooling solution at the die level. As we have discussed before [ see IFTLE xxx ] the DARPA ICECool program is divided into fundamental and applications phases with the goal of providing “… the fundamental thermofluid building blocks for the utilization of Intra and Interchip evaporative cooling in 3D DoD electronics.” It was envisioned that inter and/or intrachip cooling would be used to bring the cooling function directly to the site of the temperature rise on the device.

fig 3

Fundamental programs addressing the cooling of 3D stacks include :

GaTech / Rockwell  – STAECOOL

Click to view full screen.

Click to view full screen.

IBM / Stanford – Integrated Silicon Two Phase Cooling

fig 5

The 3D focused portion of the ICECool applications program has a goal of “enhancing the performance of embedded high performance computing systems through the application of chip-level heat removal with kW-level heat flux and heat density with thermal control of local submillimeter hot spots.”

At the December ICECool Applications kick off meeting in WDC Bar Cohen introduced the two 3D focused program winners GATech / Altera and IBM:

GaTech / Altera – SUPERCool which has the goal of bringing microfluidic cooling to the Altera FPGA.

fig 6

IBM will also participate in this phase of the contract focusing on “bringing embedded chip cooling to a high ed server and showing the extendability to 3DIC stacks.”

Click to view full screen.

Click to view full screen.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

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