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IFTLE 178 IMAPS 2013 continued: Xilinx/SPIL; Nanyang/IME; Cannon, AT&S

Finishing up our look at the fall 2013 IMAPS meeting.

Xilinx / SIliconware

We are all aware of the Xilinx / TSMC / Amkor partnership to develop the first comemrcial 2.5D FPGA module. Since that announcment in late 2010 there have been rumors about Xilinx looking for lower cost second sources. Last summer, Siliconware (SPIL) announced the instillation of a dual damascene line for fabrication of high density interposers. [ see IFTLE 158, “2013 ConFab part 2: Amkor and Siliconware”]

At the fall IMAPS meeting Xilinx and SPIL  shared results from their progra to 2.5D 28nm FPGA program.

The high performance FPGA die (it appears manufactured by UMC)  is a 4 slice 28nmchip mounted on a 25 x 31mm 100um thick Si interposer with 45um pitch microbumps. The interposer is assembled onto a 45 x 45mm organic BGA with 180um C4 bumps. The figure below shows the structure in cross section. SPIL is manufacturing the interposer and doing the assembly.

SPIL 1

Nanyang Univ / IME

Copper TSV exert thermo-mechanical stress on silicon due to the CTE miss match. This stress can result in variability of the device mobility and mechanical reliability issues. This can be alleviated by using a oxide liner that has a lower elastic modulus such as some of the “low-k” dielectric materials (black diamond). This would reduce the keep out zone and in addition such materials will lower the parasitic capacitance of the circuit.

These Singapore institutions looked at the use of low-k carbon doped oxides to serve as a more compliant layer TSV insulator layer due to its lower modulus (7.2 GPa vs plasma enhanced TEOS with modulus of 75GPa) . The FEA analysis shown below indicates that the low-K materials “should” lower the stress exerted by the Cu TSV on the silicon. Micro raman spectroscopy on samples verifies that the use of a  low-k liner results in less compressive stress exerted by the Cu TSV on the silicon between the TSV.

IME 1

CV measurements show that the capitance is reduced by 26% ( k of peteos = 3.9 vs low-K of 2.88).

[ IFTLE sees no discussion of mechanical reliability comparisons. Since low-k is known for being very fragile, I wonder whether the TSV stress will fracture the low-k material which would show up as less stress on the silicon?]

Cannon

Cannon, normally associated with front end (FE) lithography addressed “Lithography Process Optimization for 3D and 2.5D Applications.” Cannon has developed the FPA-5510iV and FPA-5510iZ TSA steppers to support high density processes and to support implementation of 2.5 & 3D technology. A comparison of their specs is shown below.

cannon 1

In a typical backside manufacturing process, patterned wafers are bonded face down to a support wafer before being ground and thinned. The bonding and thinning process causes shape distortion in the wafer. Downstream processes require litho that produces patterns that can overlay such distortions with high accuracy. These systems also employ vacuum assist functions to compensate for large wafer warpage.

AT&S / EPCOS

In July 2013 AT&S (Austria) and TDK-EPCOS announced that they were cooperating on embedding technology to allow standards development and increased customer acceptance [link].

The embedding technology developed by AT&S is shown below:

AT&S 1

The authors propose that the use of PCB real estate is lowest for an emedded component and showed the following comparison to a 3x3m die + 10 resistors packages with a QFN (45mm sq)vs flip chipped (21mm sq) vs embedded 916m sq).

AT&S 2

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  1. Pingback: Blog review February 3, 2014 | Semiconductor Manufacturing & Design Community

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