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Monthly Archives: February 2014

IFTLE 181 IEEE 3DIC contd: Tohoku Univ; Fujitsu; ASE; RTI

Finishing up on the IEEE 3DIC meeting from Oct 2013 in San Francisco lets look at some of the remaining key papers from the conference.

Tohoku Univ – Lattice Distortions in Thinned Silicon

Professor Koyanagi and coworkers at Tohoku Univ and GINTI [ Global Integration Initiative – see IFTLE 166, “IEEE 3DIC Conf part 1; 3DIC panel discussion; Ginti; Novati” ]

It is accepted that to achieve compact-sized 3DIC each functional wafer should be thinned to 50μm or less. However, the ultra-thin nature of Si substrate leads to several problems such as weak mechanical strength, warping and local deformation in the stacked die .  Moreover, the weak mechanical strength of the extremely thin die/wafer itself has a potential concern lead to die breaking for 3DIC integration, because thin LSI chip with high density TSVs is highly fragile and more easily damaged. Hence, it is important to understand the impact of chip’s mechanical strength on device reliabilities decreasing die thickness, especially below 50μm thickness.

Koyonagi and co-workers have found that the Young`s modulus (E) of Si substrate begins to noticeably decrease below 50μm thickness. The Young`s modulus in 30μm thick Si is 30% of the modulus of 50μm thickness. In 30μm Si the lattice structure is highly distorted which induces the Young`s modulus reduction and consequently weakens the mechanical strength.

1

DRAM chip of 200μm thickness were bonded to a Si interposer and thinned down to 50, 40, 30 and 20μm respectively. The measured retention characteristics of DRAM cell on these thicknesses of silicon are degraded dramatically below 50-μm thickness, i.e. the retention time of DRAM cell in 20μm thick chip is shortened by approximately 40% compared to the 50-μm thick chip.

2

They assume that the band-gap energy in the thin chip is affected by the distortion of the lattice structure, hence effect on a minority carrier lifetime, consequently shortening the retention time of DRAM cell.

Fujitsu – Influence of Wafer Thinning on Backside Damage

Fujitsu is known for their ultrathin WOW process [ see  “Development of Multistack Process on  Wafer-on-Wafer (WOW)

Ultra-thinning to 10 microns or less of Si wafer is expected to realize small TSV with low aspect ratio and coupling capacitance. Subsurface damage following wafer thinning from the back of 300 mm wafers using three different types of thinning process was investigated by means of Raman spectroscopy, XTEM, and Positron annihilation analysis, respectively. A coarse grinding generates significant rough subsurface ranged several micron and damage layer including amorphous and plastic-deformed Si along grinding topography. Fine grinding, second step of thinning, reduced those surface roughness and almost removed after thinning at least removal of 50 microns. However, plastic-deformed subsurface layer with a thickness of 100 to 200 nm are still remained which leaves an inside elastic stress layer ranging up to about 10 microns in depth. Chemical-Mechanical Polishing (CMP) process as a final step of thinning enables to remove residual damages such as structural defects and lattice strains after 1-5 microns thick polishing while vacancy-type defects only remain.

3

The authors acknowledge that further investigations are necessary to find “hidden residual defects” and to understand the influence of thinning on memory devices (see Tohoku discussions above).

ASE / Chiao Tung Univ – Low Temp Bonding

ASE and National Chiao Tung Univ  have studied three types of bonding, including Cu-In, Sn/In-Cu, and Cu/Ti-Ti/Cu, for application of 3D interconnects.

Cu-In bonding and Sn/In-Cu bonding can form intermetallic compounds at the bonding temperature lower than 180 C. Cu and In samples were bonded face-to-face with a bonding pressure of 1.91 MPa, followed by a heating temperature of 170 C for 50 min. Sn/In and Cu samples were bonded face-to-face with a bonding pressure of 1.91 MPa, at bonding temperature of 180 C for 50 min.

Cu/Ti samples were bonded face to face with a bonding pressure of 1.91 MPa, at a heating temperature of 180 C for 50 min.  They add that Cu can be protected from oxidation by capping Ti on Cu surface before bonding. This last structure is especially significant if one can really do such bonding at 180 C . Their EDX investigation of the interface shows that “…apparently there is a Cu layer at the bonding interface instead of Ti layers…due to lower activation energy at the surface, Cu tends to diffuse towards the surface  …”  IFTLE feels this combination certainly deserves further study.

All bonded structures have shown excellent electrical performance and reliability characteristics. Based on bond results, these structures can be applied for low temperature bonding in 3D interconnects.

RTI – 10um Pitch Bonding of Hetero Materials

Matt Lueck of RTI Int described their successful demonstration of the use and reliability of Cu/Sn microbumps for the fine pitch interconnection of heterogeneous semiconductor die. InP die have been bonded to Si substrates using a 6.4 mm × 5.12 mm area array of alloyed Cu/Sn microbumps on 10 μm pitch.

A key technological challenge facing the 3D integration of heterogeneous semiconductors is the formation of high density metal interconnects between dissimilar substrates, such as compound semiconductors (CS) and Si. Due to the difference in the coefficients of thermal expansion (CTE), one can expect: 1) some misalignment between microbumps fabricated on the CS substrate and the Si substrate during bonding at an elevated temperature; and 2) bond interconnects will experience shear strain as the bonded die pair is cooled to room temperature and during any subsequent thermal excursions.

4

To estimate the magnitude of the misalignment, they calculated the relative change in distance between corner microbumps in a 10 μm pitch 640 × 512 array on CS die vs. Si die. Operability was determined by electrical testing of long daisy-chains of bumps.

The average channel yield was approximately 97% for both InP-Si and Si-Si die pairs translating into the array operability greater than 99.99%. The reliability of InP-Si and SI-Si die pairs was compared after 500 thermal cycles of -40 – 125 C. No significant change in yield was seen for the homogeneous Si-Si die pairs. The InP-Si die pairs that were underfilled showed a 2.8% decrease in channel yield whereas those not underfilled showed a 13.9% decrease.

5

They conclude that Cu/Sn micro bumps can be successfully and reliably used for integration of InP and Si die.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 180 GaTech Interposer Conference

Continuing our look at the 2013 GaTech Interposer Conference.

CORRECTION to IFTLE 178:

A reader has written in to indicating that the FPGA chip described in the Xilinx/SPIL paper was fabricated by TSMC not UMC .

Corning and Schott Glass

As discussed in IFTLE 170, Windsor Thomas of Corning gave a presentation entitled “The manufacturing readiness of Glass interposers” and Schott glass followed with a presentation entitled “New Ultra-thin Glass for Microelectronics.”

Since the whole LCD infrastructure is based on thin glass we certainly did not need any convincing that large panel, uniform, thin glass is available in roll and/or large panel format. Corning like Asahi Glass and Schott glass has been researching the formation of TSV (or TGV) for several years now and all appear somewhat able to form through vias down to maybe 25um. The real question is how do we than use this feedstock to get low cost glass interposers.

Though we were shown some Cu fill experiments, neither Corning nor Schott  indicated that they would enter the interposer market, did not indicate who such a partner would be and in fact stated that their discussions with the FPD industry( which they most certainly now supply) indicate that there is absolutely no interest in FPD suppliers entering the interposer supply market.

IFTLE concludes that if any of the current glass suppliers want to see glass become a interposer substrate material and more broadly a preferred packaging substrate material, they must resolve who will actually be supplying the final packaging products.

Asahi glass has attempted to fill this void with Triton, their JV with nMode [see IFTLE 141, “100GB Wide IO memory; AGC Glass Interposers; Nvidia talks stacked memory” ] Corning and Schott have not yet indicated what their proposed solutions are.

Shinko

Koizumi-san  of Shinko discussed glass substrate prototyping status. Shinko points out that glass cores can be used to mimic Si like interposers or build-up PCB substrates.

Shinko1

He showed data on a 200um glass core PCB with a 5/0/5 build up process ( 30um polymer/18um thick Cu per layer) . When diced such structures resulted in what they called “Se-wa-re” (loosely translated back split) which was fracture through the glass core layer due to the stresses built up on both sides of the core. Modeling calculations show that the glass internal stress is mainly caused by the total copper layer thickness.

shinko2

Altera

John Xie of Altera examined the use of organic interconnect for stacked die integration.  Altera’s take on Interconnect resolution trends are compared below. The proposal is that organic build up (BU) substrate (dry processed) is rapidly approaching the capabilities of this film BE of line packaging on silicon.

Altera 1

Xie contends that high end substrate suppliers are quickly approaching 2/2 L/S and will allow direct attach to substrate and elimination of the interposer as shown below. This in turn will be a cost reduction driver. He calls this 2.1D or Ultra high density organic  interconnect. They can currently get 92um bump pitch, 8um lines and 80um vias. Their 2 year goal is to obtain 55um bump pitch, 2um lines and 20um vias.

Altera 2

Zeon

Zeon introduced their ultra tine dry films for Interposer RDL applications. Properties of the Zeon “cyclo olefin” polymer film are shown below.

Zeon 1

Ushio

Ushio addressed large area litho tools for 1 – 5µm  L/S. They claim their tool is capable of 2µm L/S in a 70 x 70 sq mm area.

Sohio 1

For all the latest on 3DIC and advanced packaging stay linked to IFTLE…

IFTLE 179 GaTech Interposer Conf: Amkor, GlobalFoundries

Continuing our look at the 2013 GaTech Interposer Conference.

Amkor

Ron Huemoeller of Amkor addressed interposer use, defining the markets and materials options as follows:

Amkor 1

Amkor projects that in the high end silicon will dominate; in the mid-end, silicon will be prominent and organic /glass may play a role; in the low end, organic, or low cost glass or silicon if they exist will play a role.

Silicon Interposers

Product Applications

- Gaming, HDTV, mobile tablets, computing, servers

- High end graphics cards will be the initial focus of HBM memory integration

- mobile space has the potential to follow based on availability of low cost solutions

 

Visible and Anticipated Demand

- continued low volume production of FPGAs and ASICs

- moderate volumes for high end graphics cards; HBM cost/availability driven

- high volumes for mobile; interposer cost driven at less than $0.01 per sq mm.

 

Market Longevity

- expect to have a very long life cycle

- long term continued use through deconstruction of very high end node logic to address system level cost and power related memory integration issues.

Amkor describes the silicon interposer supply chain

-  Current

- TSMC – not supplying to the industry

- UMC and Global Foundries – both have limited capacity and neither desires to be a merchant supplier

- Future

- Yet unannounced merchant supplier

- use of depreciated equipment and excess capacity

- lowers cost vs tier 1 foundries

- supply interposer without desire to bundle chip fab.

Organic Interposer Sources:

- Tier 1 Shinko, SEMCO

- 2/2 (L/S) 10/22 (via/pad); very limited sampling

- Tier 2 Kyocera

- 5/5 (L/S); 18/30 (vias/pads); very limited sampling

- Tier 3 Kinsus, Unimicron

- early development

 

GlobalFoundries

Dave McCann of GlobalFoundries examined market needs for interposers. McCann used the latest Gartner data on SoC costs to point out that development costs for a 10nm design are expected to approach $400MM.

GF1

GF again made the case that “DIS-integration” can actually offset scaling costs, i.e.:

GF2

GF indicates that the yield of high density interposers is high (“..approaching 100%”), even for  full retical sized; 4 metal layer top side, 1 metal layer backside structures.

GF has come up with the following roadmap for silicon, high density laminate and glass.

GF3

Like Amkor, GF has mapped 2.5D requirements by market space and come up with the following.

GF4

Also similar to Amkor GF pointed out that the industry needs a low cost high volume source of  high density interposers. Although showing their capabilities for interposer fabrication, interestingly they did not offer themselves up as the solution.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.