By Dr. Phil Garrou
For several years now through PFTLE (in Semiconductor Int) and IFTLE (in Solid State Technology) I have been mimicking Kareem Abdul Jabbar’s role as the street preacher in Stephen King’s “The Stand.” For those of you who have not seen the movie (or read the novel) he marches through Times Square ringing a big cow bell and wearing a sign reading “The End is Near.” He is predicting the end of the world as we know it due to a plague released by a secret Government lab. No one believes him, but soon, as they all begin die, we become aware that he was correct.
I have not been predicting the end of the world, but rather the end of electronics as we know it, i.e relying on CMOS scaling. Similar to my economic prediction that the stock market will “soon” fall, sooner or later I will be right. Therefore, it was with great anticipation that I perused the 2013 ITRS roadmap that was released a few weeks ago. Would they try to ignore what is happening or would they face the issue head on like the poet of my generation Bob Dylan who in 1964 released “The times they are a-changin”. I am happy to tell you they are facing the challenges head on although the ultimate solutions are, as we might expect, not yet crystal clear.
The 2013 ITRS Roadmap
The ITRS for those of you not familiar with the group is jointly sponsored by the US, Taiwan, European and Korean SIA and the Japanese JEITA (Japan Electronics and Information Tech Industry Assoc) so they are certainly “mainstream.” Hundreds of technologists from around the world staff the dozens of committees that every few years update where the semiconductor industry is going.
A quick look at the Exec Summary gives us a good understanding of the theme for this update “The ever changing environment.” They contend that the Semiconductor Industry, born in the 70s, had two main goals: (1) providing cost effective memory devices with pin-out and functionality standardization and (2) application specific integrated circuits (ASICS) that required specific functionalities to realize novel products.
In the 80s system specifications were in the hands of the system integrators. Through scaling, semiconductor technologies were introduced every three years by memory devices and were subsequently adopted by makers of logic devices. In the 90s continued scaling allowed logic and memory IC manufacturers introduced new technologies every two years and substantial part of the control of system performance and profits moved into the hands of IC manufacturers. This period of ~25 years can be called the Era of “Classical Scaling.”
In the late 1990’s we began to see technologies such as strained silicon, high- κ /metal-gate and multigate transistors be used to further improve device performance. This second Era known as the Era of “Equivalent Scaling” That can be seen in the figure below [ this is not in the ITRS roadmap, IFTLE added it to strengthen the point]
3D Power Scaling
Because 2D scaling will eventually reach fundamental limits, both logic and memory are now exploring the use of the vertical dimension (3D). Increase in the number of transistors per unit area will eventually be accomplished by stacking multiple layers of transistors. The combination of 3D device architecture and low power device will usher the (Third) Era of Scaling, “3D Power Scaling.”
System integration has shifted from a computational, PC centric approach to a mobile communication approach.
The heterogeneous integration of multiple technologies in a limited space (e.g., GPS, phone, tablet, mobile phones, etc.) is now the main goal of any design from a performance driven and reduced power driven approach. In the past performance was the only goal; today power consumption drives IC design.
The foundation of heterogeneous integration relies on “More Moore” (scaling) devices with “More than Moore” elements that add new non CMOS functionalities that do not typically scale or behave according to “Moore’s Law.”
Unfortunately the sections of the report that are of the most interest to IFTLE namely back-of-the-line “Interconnect” and “Assembly & Packaging” are evidently not completed (or cleared for publication) yet. So discussion of those sections will have to wait. We have been given a glimpse of the packaging and assembly challenges in the table shown below.
The full report (all that has been released thus far) can be found here [link]
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