We have all been waiting a long time to see the following headline:
Intel to Commercialize HMC Stacked Memory – Knights Landing
Last week at the 2014 ISC (International Supercomputing Conference) it was announced that the Intel Xenon Phi processor “Knights Landing” would debut in 2015. [link] It will be manufactured by Intel using 14nm FinFET process technology and will include up to 72 processor cores that can work on up to four threads per core. It will support for up to 384 GB of on board DDR4 RAM and 16GB of Micron HMC stacked DRAM on-package, providing up to 500GB/sec of memory bandwidth. It will be the first Intel processor to use this new high performance on package memory.
The Micron 3D stacked memory which we have know as the hybrid memory cube for several years is being called “multichannel memory or MCDRAM. Micron reports that having such memory in the CPU package is expected to deliver 5X the sustained memory bandwidth versus GDDR5 with one-third the energy per bit in half the footprint.
Knights Landing is expected to be deployed in various high performance computing solutions such a as the Cray “Cori” at National Energy Research Scientific Computing (NERSC) Center.
Long time IFTLE readers recall that Intel was involved from the beginning with the concept of HMC [ see IFTLE 74, “The Memory Cube Consortium” ] and in fact shared a glimpse of the memory cube technology at their developers forum in June of 2011.[link]
Recall Micron contracted IBM to manufacture the logic interface layer [see IFTLE 95, “3DIC – Time Flies When You’re Having Fun; Further Details on the Micron HMC….”]
So it was interesting to see the logic layer on display recently in the IBM booth at ECTC. I’m pretty sure this is it (before the memory layers are attached).
While the excitement level around this announcement will be high, we should all understand that as described this is a high end HPC application, not the high volume driver that the 3DIC world has been awaiting. The question for intel is will Intel use this as a platform to compete with nVidia and AMD/ATI on graphics, or will this be just a niche HPC product?
We should also note that although Intel has numerous patents in the area, there is no current indication that this will be a 2.5D solution. Intel has thus far only said “it will be high bandwidth.”
Anyone else surprised by the recent announcement that GS Nanotech (Kaliningrad, Russia) “plans to launch mass assembly of 3D stacked TSV microcircuits in the next few years”? I must admit I had never heard of them. A quick look at their web page indicates that they manufacture chips for General satellite set-top-boxes and have ST Micro, Nanium, Toshiba and Winbond listed as customers.
FYI – we are in the process of inviting them to speak at the RTI ASIP conference in December to see exactly what they have and what their plans are.
From our friends at Digitimes: “STATS ChipPAC, the world’s fourth-largest IC backend service company, has put itself up for sale with ASE, Changjiang Electronics Technology, Samsung and Huatian Technology (Xian) likely to compete for the sale… STATS ChipPAC has been holding talks with potential buyers since mid-May, with ASE and Changjiang being the first two contenders… Changjiang aims to enhance its manufacturing technology and patent portfolio, and to ramp up total capacity by acquiring STATS ChipPAC, noted the sources… ASE’s bid for STATS ChipPac is more likely to prevent other potential competitors from taking over STATS ChipPAC to build up capacity against ASE…” Samsung, Huatian, Foxconn, UTAC and GlobalFoundries have also been rumored to be potential acquirers. [link]
For all the latest on 3DIC and other advanced packaging solutions, stay linked to IFTLE…