Insights From Leading Edge

Monthly Archives: August 2014

IFTLE 206 COSMOS and DAHI Herald the Era of 3D Heterogeneous Integration

By Dr. Phil Garrou, Contributing Editor

For about a decade now, we have been awaiting the full commercialization of 3DIC. From the beginning most practitioners laid out a roadmap where CMOS Image sensors led the way followed by memory stacks, memory-on-logic, logic on logic and lastly the holy grail of heterogeneous integration where we could combine advanced semiconductor materials and different  functions, with high-density silicon CMOS technology.

Indeed CMOS image sensors have led the way [ see IFTLE 199,  “Omnivision Roadmaps 3D stacking for CMOS Image Sensors…” ] and DRAM memory stacks from Hynix and Micron are on the verge of full commercialization [ see IFTLE 202, “ConFab 2014: Novati, Lumileds; Chipworks; IEEE CPMT Packaging Panel”].

A lesser publicized fact is that we are actually very close to functional heterogeneous integration thanks to the efforts of many participants in the DARPA sponsored COSMOS and DAHI programs.

The development of non SI based semiconductor (compound semiconductors, CS) electronics has been motivated by their superior materials properties relative to silicon. For example, high electron mobility and peak velocity of InP-based material systems have resulted in transistors with fmax above 1THz. The wide energy bandgap of GaN has enabled large voltage swings as well as high breakdown voltage RF power devices and the excellent thermal conductivity of SiC makes tens of kilowatt-level power switches possible [1]

[1] S. Raman, “The DARPA Diverse Accessible Heterogeneous Integration (DAHI) Program: Towards a Next-Generation Technology Platform for High-Performance Microsystems”, 2012 CS Mantech Conf.

DARPA proposes  that the future of CS electronics depends not on displacing Si, but rather on heterogeneous integration of compound semiconductors with silicon technology in a way that will take advantages of the two technologies when combined.

Past attempts at heterogeneous integration has been at the module level, i.e Multichip Modules [see “Multichip Module Technology Handbook” , P. Garrou, I Turlik Eds., McGraw Hill, 1998].

However, MCM techniques have been limited by I/O parasitic effects between chips in such modules and by device and interconnect variability issues. Many of the limitations including I/O parasitics and phase mismatch are governed by the length of separation between CS and Si CMOS devices, and as such, reduction of this separation is expected to yield dramatic improvements in performance of heterogeneous integrated circuits.

The COSMOS [ Compound Semiconductor Materials on Silicon] program began in 2007 with teams led by Northrup Grumman, Raytheon and HRL (Hughes Research Labs).  They have demonstrated three different approaches (see below) to achieving InP BiCMOS integrated circuit technology featuring InP HBTs and deep submicron Si CMOS for RF and mixed signal circuits.

COSMOS

 

The Northrop Grumman technology starts with a completely fabricated standard CMOS wafer. A separately fabricated InP HBT wafer (thinned to approximately 55u m) is mounted to a glass carrier. An InP wafer is etched to form individual chiplets (still attached to the carrier wafer). The CMOS wafer is prepared for integration with the InP chiplets by depositing gold (Au) micro bumps (3-10um and 2um thick). The glass carrier containing the singulated InP chiplets is then aligned to the CMOS wafer, and the bonding operation performed using standard wafer bonding equipment with controlled time, temperature, and bonding force. The glass carrier wafer is then released, leaving the singulated InP chiplets connected to the base CMOS wafer. This is shown schematically below.

NG

 

DARPA is also pursuing the integration of GaN transistors with Si CMOS on a Si substrate.  For example. the Raytheon team has recently demonstrated a monolithically integrated RF amplifier circuit  using heterogeneously interconnected GaN HEMTs and pMOS gate bias control (see below).

Raytheon GaN

 

DAHI (Diverse Accessible Heterogeneous Integration)  initiated in 2013 is based on its predecessor COSMOS and is composed of several design, technology and manufacturing thrusts including :

  • Si CMOS for highly integrated analog and digital circuits
  • GaN for high-power/high-voltage swing and low-noise amplifiers
  • GaAs and InP HBT and HEMT for high speed/low-noise circuits
  • Compound semiconductor optoelectronic devices for direct-bandgap photonic sources and detectors, as well as or silicon-based structures for modulators, waveguides, etc.
  • MEMS components for sensors, actuators and RF resonators
  • Thermal management structures

Program teams include:

  • Teledyne/Tezzaron/UC Santa Barbara
  • MIT/Raytheon/Stanford
  • IBM/Columbia U/MIT/Veeco
  • NG/Novati/Nuvotronics/MOSIS/ON Semi
  • HRL/ UC San Diego/U Mass/U FLA
  • Raytheon/Novati/IBM
  • Rockwell/Tower Jazz/UCSD

At the recent DAHI program review in Boulder participants shared their technology progress to fabricate multilayer circuit structures (i.e InP, Si, GaN) on substrates such as SiC using 3DIC technologies such as TSV and oxide-oxide bonding.

The  goal of DAHI is to establish a manufacturable, accessible foundry technology for the monolithic heterogeneous co-integration of diverse (e.g., electronic, photonic, MEMS) devices, and complex silicon-enabled architectures, on a common substrate platform for defense and commercial users. By enabling the ability to ‘mix and match’ a wide variety of devices and materials on a common silicon substrate, circuit designers can select the best device for each function within their designs.  This integration would provide DoD systems with the benefits of a variety of devices and materials integrated in close proximity on a single chip, minimizing the performance limitations caused by physical separation among devices.

As these technologies become public, IFTLE will keep its readers apprised of the results.

For the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 205 2014 ECTC part 1: Controlling Warpage in Advanced Packaging

By Dr. Phil Garrou, Contributing Editor

We are a bit out of chronological sequence, but as usual the ECTC was chuck full of materials worthy of coverage. Since the presentation is in six parallel sessions it takes time to go back and read all of them, and, since the papers are published in IEEE Explore, I do not have the power point presentations to summarize for you.

Let’s start off with some papers concerned with warpage issues.

Hitachi Chemical

As we continue to miniaturize, warpage remains the main problem encountered in all areas of advanced packaging. Kotake of Hitachi Chemical addressed “Ultra low CTE core materials for next generation thin CSPs” They describe ultra low CTE (1.8) core materials (E-770G) which are used to reduce warpage in PoP packages. Hitachi simulations show that the CTE of core materials has more impact that the modulus.

Hitachi 1

 

Best results are obtained when using the new material E-770G for both core and prepreg.

Amkor

Kim and co-workers at Amkor reported on “Strip grinding Introduction for thin PoP.” Typical PoP used in mobile products consists of a logic function In the bottom package and a memory function in the top package. The most difficult barrier to fabricate the thin PoP is warpage control. Amkor TMV (through mold via) PoP structures can be overmolded or exposed die (to allow for heat sinking). When trying to thin the package, there is a limit to the  thinness of the overmold and a limit to the silicon die thickness since thinner die result in die chipping or cracking during handling. In the thin mold cap case, it’s not easy to control the package warpage. The warpage can be controlled with a thicker substrate, but this increases the package thickness.

The concept of strip grinding is to grind the mold compound and die together. The advantage of strip grinding is to use normal die thickness and mold cap thickness, thus reducing the risk of thin die handling and narrow mold clearance. Mold flash is eliminated through the grinding methodology. By applying a strip grinding process, we can easily generate a very thin die and mold cap.

amkor 1

 

Double side molded structures are possible, which help make a balanced structure on top and bottom which tends to improve the warpage performance. Bottom side mold is difficult, because the BGA ball is mounted on the bottom area.

For the double-sided mold process flow, chip attach on the top side and BGA ball attach on the bottom side need to be done first followed by double side mold. The bottom molding is ground until the bottom ball is exposed. To remake a BGA, a second ball attach needs to be performed to generate a proper BGA standoff.

amkor 2

 

Warpage simulations were done for a variety of die/substrate/mold thicknesses, as shown below.

amkor 3

 

Warpage is minimized when (a) thin die is double-side molded, i.e leg 6; (b) very thin die i.e leg 3 or (c) thick substrate to balance mold, i.e leg 1.

Qualcomm

Bchir of Qualcomm discussed “improvement of substrate and package warpage by copper plating optimization.”

While substrate warpage is typically approached through modification of dielectric material properties (such as CTE, Tg, modulus), layer thicknesses (core, prepreg, solder resist and Cu thickness), and Cu areal density per layer there is also an impact from the Cu plating process. Electroplated Cu thin films have porous grain boundaries, wherein grain boundary volume is strongly dependent on electroplating conditions and subsequent thermal processing.  During thermal processing, Cu grains grow and merge, eliminating grain boundaries and causing shrinkage. The residual stress in the initial deposit, coupled with shrinkage during subsequent thermal processing, strongly impacts the warpage of the substrate and package. This is compounded by the inherent front-to-back Cu density imbalance which is typical in substrate design.

Choice of electrolytic Cu plating solution has significant impact on the magnitude of package warpage. The influence of Cu plating solution on warpage is related to the resulting grain size distribution and stress state deposited from a given chemistry. Plating additives can be co-deposited as impurities into the Cu layer, and have been shown to strongly impact residual stress and grain coarsening behavior of the Cu deposit.

They found that reducing the plating current density for a given plating solution led to substantial reduction in package warpage. Also,  an increase in the plating current density causes a reduction in the deposited grain size, hence a reduction in current density would lead to larger deposited grains and thus larger grains would mean reduced grain boundary volume, less “shrink” in the Cu layer and lower residual stress in the Cu.

IMEC

Eric Beyne’s group at IMEC detailed their work on “Minimizing Interposer Warpage by Process Control and Design Optimization.” Imec’s silicon interposer technology consists of 10×100μm TSV, four thick damascene BEOL layers, Cu bumps and redistribution layers (RDL) front side and back side.

IMEC 1

 

They calculated and measured 300mm wafer bowing at different stages of interposer BEOL processing, as shown below. There is good agreement between simulation and measurement. For a 10mm x 20mm interposer, bowing is measured as 30um (short side) x 130um.

IMEC 20

 

Bowing mitagation was investigated by:

-  Replacing standard Pre-Metal-Dielectric (PMD) layer by a thicker and more compressive insulator

- The use of thinner Metal1 and Metal2

- The use of a more compressive oxide in the BEOL

- Replacing the standard PMD layer (300 nm/80 nm SiO/SiC layer) by a thick PECVD oxide with -170 MPa compressive results in a bow reduction of around 150 um (-37% bowing).

At die level,  bowing value of around 45 μm (-59% bowing) is predicted by the model for a 20 x 20mm  interposer.

IMEC 3

 

The use of thinner Metal1 and Metal2 will increase the sheet resistance of the two layers and consequently may impact the electrical performances of the interposer. The figure below shows that reducing the thickness of M1 and M2 effectively reduce the bowing and that a thickness of around 0.4μm could be a good trade-off between bowing and performance decreases.

IMEC 4

 

Small modification of the stress of the oxide can be very efficient to decrease the bowing at wafer but also thin die level.

IMEC 5

 

They conclude that “the use of a more compressive and thicker PMD insulator layer, a reduction in Metal1/Metal2 thickness, the use of more compressive oxide within the BEOL, are promising and easy to implement solutions to reduce interposer bowing with a limited impact onto its performances.”

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 204 IBM / GF Semi Deal: the drama continues; Leti Studies Monolithic 3D

By Phil Garrou, Contributing Editor

Reports a week ago indicated that “It appears that IBM’s sale of its microchip manufacturing business to GlobalFoundries had fallen apart.” [link]

The local paper, the Poughkeepsie Journal, citing “anonymous sources with knowledge of the inner workings of IBM”, said the deal had been known under the codename  “Project Next.” Reportedly IBM managers at East Fishkill were told July 15th that the deal to sell its microchip unit to GlobalFoundries was off. The Journal quoted consultants who felt that such a deal would likely need clearance from federal agencies since IBM is a so-called “trusted foundry” for the U.S. military and GlobalFoundries is owned by the government of Abu Dhabi [link].

Perhaps, but…

 Bloomberg reported on Aug 5th that “according to a person familiar with the process”, it was  IBM offering to pay GlobalFoundries to take on IBM’s money-losing chip-manufacturing operations [link].

According to Bloomberg contacts, IBM was offering about $1 billion to entice Globalfoundries to take the unit but  Globalfoundries wanted $2 billion. Recall it has been reported that the IBM Semi business has been losing ~ $1.5B / year for several years.

It is likely that IBM requested GF continue operation of the two facilities to maintain supply of chips that they are using in IBM products. To do so GF would likely continue to incur similar losses and that may have outweighed acquisition of whatever IBM IP was to be included in the deal. IFTLE’s  understanding is that Burlington could be made to operate as an analog / specialty division, but East Fishkill (which reportedly cost $2.5B to build) should just be closed down because it is old and outdated.

With IBM semiconductor employees understanding that their division is no longer wanted by IBM corporate, many are jumping to GlobalFoundries which is actually setting up “job fairs” in the IBM factory communities [link].

It appears to IFTLE that IBM does not have much leverage in all of this, but we will see as the drama continues.

Leti Continues to Study Monolithic 3D

In Dec 2013 Qualcomm, in a move that appeared to show impatience with the development of 2.5/3DIC infrasructure, announced an agreement with CEA-Leti, to assess the feasibility and the value of Leti’s sequential (monolithic) 3D technology. In comparison with 3D-TSV technologies which  stack separate die, sequential 3D technology proposes to process all the functions in a single semiconductor manufacturing flow. Thus, the technology allows connecting active areas at the transistor level, at a very high density as it uses a standard lithography process to align them.

According to Leti, this technology is expected to produce a 50% gain in area and a 30 percent gain in speed compared to the same technology node in 2D. They expect the  sequential 3D technology will be much less complex and expensive to implement than sub 22nm nodes , making this technology a potential alternative to conventional planar scaling.
At the recent Semicon West event in San Francisco, Olivier Faynot, devices department director at CEA-Leti updated the community on their results thus far. According to Faynot the design kit is ready since technology is standard CMOS processing.

Leti 1
As expected, the issues are all thermal due to the sequential processing.

leti 2

It is hoped that advanced laser processing will allow proper dopant activation without disturbing lower layers.

Leti 3

 

They report that initial results show thermal stability demonstrated up to 500°C at 28nm and 14nm SOI nodes.

Key points ae reportedly silicide stability and dopant deactivation for NMOS.  On going process work includes:

• W implantation    • NiPt deposition    • Silicide formation    • F implantation

• RTP at various durations and T°

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 203 Apple Acquires LuxVue µ-assembly Technology

By Dr. Phil Garrou, Contributing Editor

Apple has acquired 24 tech companies in the last 18 months. Recently, Apple acquired LuxVue, a start-up focused on low power micro-LED displays. Although Apple has not disclosed any details of the acquisition, not even the purchase price, one can easily envision where micro LED displays could play a big part in Apples thrust into wearable electronics such as the i-watch. Reportedly the LuxVue display is 9 times brighter than both LED and LCD screens.  Such µ LED displays would be compatible with curved surfaces and would save power and thus increase battery life. Brighter, lower power displays could have applications in other Apple products and products such as Google glasses.

Little is known about the LuxVue technology other than the patents that have been issued. They have no web page and have made no public presentations that I can find. The do have several dozen patents many of which deal with transferring micro devices, which specifically for displays would be LED devices as small as 10 x 10 miron and placing them on 10 micron pitch.

Their preferred transfer device consists of a substrate with an arrangement of protruding mesas. Each mesa contains electrodes with a thin coating of dielectric. By providing a charge between the electrodes, an electrical field is created which electrostatically attracts the miniature chips or LEDs [for example, see USP 8333860 B1].

It is proposed that using this approach one can selectively choose to remove specific micro devices from a source substrate by applying voltage only to the projecting mesas corresponding to the positions of the device to be transferred.

In essence, this is massively parallel pick and place. We are all familiar with conventional pick-and-place assembly using vacuum collets and pin ejectors. For devices that are on the scale of 10 micron however, manipulation and accurate placement are significantly more difficult with today’s tools. This LuxVue “electrostatic chuck” mechanism is one way to deal with manipulation of such small devices.

If massively parallel pick-and-place sounds familiar, recall similar technology Semprius and more recently X-Celeprint have been developing.  These startups are based on the work of John Rogers at U. Ill. Which uses PDMS stamps rather than the more complex electrostatic chuck. [link 1] [link 2]

I have compared the two technologies in the figure below:

Xceleprint vs luxvue

 

I contacted Professor Rogers and X-Celeprint CTO Chris Bower, and they agreed that microassembly of such LEDs is indeed the sweet spot for X-Celeprint technology. They sent the images below which show some early examples of transparent and flexible devices using Micro-Transfer-Printed inorganic LEDs. At this point, they were just willing to say that this was an area “of active interest.”

Double printing the RGB LEDs allows circuit redundancy, so a bad LED or connection does not produce a bad pixel. This is the technique already in use by display manufacturers [link 1] and more recently 3DIC practitioners to insure that a bad TSV does not result in a failed chip [link 2].

REPLACE

As devices continue to get smaller, we can expect to see micro transfer technologies such as these take a more prominent role in their assembly.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…