Insights From Leading Edge



IFTLE 311 SEMICON Taiwan Part 5: Packaging at TSMC

By Dr. Phil Garrou, Contributing Editor

Continuing our look at advanced packaging activity at the 2016 Semicon Taiwan. This week we finish our overview of Semicon Taiwan 216 with an examination of presentations by TSMC who as we all know is making a major push into the high end packaging market.

TSMC – Packaging Solutions

Doug Yu discussed TSMC packaging solutions which are summarized below:

TSMC 1

The history of TSMCs CoWoS interposer commercialization is shown below. CoWoS “key merits” include:

Sub-mm interconnect

  • DD Cu, 1000+ lines/mm
  • Small via, easy routing
  • Very low defect density

Super large size

  • 1200 mm2 in production. Going 1500 mm2
  • Highest level of multi-die integration

TSMC 2

Multichip InFO vs multichip FC CSP are compared below:

TSMC 3

TSMC – Interposers Past, Present and Future

Shang Hou of TSMC discussed interposers past, present and future.

Hou compared the TSMC CoWoS TSV based interposer technology to TSMC InFO fan out packaging in the slide below. The first gen CoWoS started in 2012 with 28nm logic chips. The industry’s first 16nm network processor was built with CoWoS® in (2014). CoWoS delivers faster time-to-market by eliminating the node-dependent CPI seen in conventional packages.

TSMC Hou 1

2nd Gen CoWoS

The industry’s first 20nm FPGA product was built on CoWoS in 2015

  • xtra large interposer ~1200 mm2
  • Composed by two-masks stitching of sub-micron RDL
  • Package with record-large chip size
  • Passed stringent component reliability tests

TSMC Hou 2

Volume is by far the No.1 factor in the cost equation

  • It has not yet find a niche in mobile applications
  • There is firm demand in the extremely high-end market (Cloud)

Interposer high intrinsic cost is unavoidable compared with flip chip. The key is whether it has sufficient value to justify the cost?

For all the latest on Advanced Packaging stay linked to IFTLE…

 

 

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