By Dr. Phil Garrou, Contributing Editor
Back in the late 1970s, there was a TV show in the US called ChiPS which stood for California Highway Patrol. It was poorly written and even more poorly acted. Thank goodness that’s not what we are going to be talking about now.
The research wing of the Defense Department, otherwise known as DARPA, put out a broad agency announcement in Sept 2016 for a program called “Common Heterogeneous Integration and IP Reuse Strategies with the same acronym, CHIPS [BAA-16-62] with an anticipated funding level of ~ $70MM. Multiple award are expected. Final proposal due date was Dec 16th and the estimated start date was reported to be ~ 4 months after proposal submission. The program is being run by Dr. Dan Green in MTO (Microsystems Technology Office).
Pay attention to this program because it has the possibility of creating a paradigm shift in how electronics are done today. The goal is to lower cost and decrease turn around time for military electronics, but design flows that will be created could have major impact on the industry as a whole. As IFTLE has said in the past few weeks, with the end of Moores Law, we are searching for high impact alternatives and this just may be it.
As the BAA describes it, DARPA expects participants to “…leverage existing designs that would benefit from translation to a modular framework in order to enable reuse of captive IP, include commercial IP, or allow faster redesign and update cycles.” A key feature of CHIPS is the establishment of standard interfaces to promote the reusability and interchangeability of modular circuit functional blocks or chiplets. In the first phase of the program the community will “converge on a limited number of interface standards that are broadly useful.”
CHIPS consists of 3 technical areas (TA1) focused on modular digital designs; (TA2) focused on modular analog design and (TA3) focused on supporting technologies.
SoC (system on chip) technology has been driving the industry for several decades as further functions were implemented on chip. We are now looking at a reversal of this process. DARPA called it “dis-aggregation” IFTLE prefers to call it “disintegration”. Once in place it wil allow you to replace only functions that need to be upgraded and not have to redesign and remanufacture the whole SoC chip. Whatever you want to call it, it looks like exciting times are ahead and you will be sure IFTLE will keep you informed on all new CHIPS info as it becomes public.
Amkor Acquires Nanium
OSAT consolidation continues as Amkor and NANIUM have announced that they have entered into an agreement for Amkor to acquire NANIUM. NANIUM is based in Porto, Portugal, has 500+ employees and sales of ~ $40 million in 2016. Terms of the transaction were not disclosed.
“Amkor’s technology leadership, substantial resources and global presence coupled with NANIUM’s best-in-class WLFO packaging solutions will accelerate global acceptance and growth of this technology worldwide.”
The acquisition of NANIUM will strengthen Amkor’s position in the fast growing market of wafer-level packaging for smartphones, tablets and other applications. NANIUM has developed a high-yielding, reliable eWLB based WLFO technology, and has successfully ramped that technology to high volume production. NANIUM has shipped ~ 1B WLFO packages off their 300mm Wafer-Level Packaging (WLP) production line.
Adding this to their SLIM and SWIFT technologies which are moving into HVM Amkor seeks to expand the manufacturing scale and broaden the customer base for such fan out technology solutions.
GE Licenses SEMCO their Embedded Chip Packaging Technology
GE Ventures and Samsung Electro-Mechanics (SEMCO), have announced a patent license agreement where SEMCO will license GE microelectronics packaging patent portfolio, covering the fabrication of substrates embedded with electronic circuits. This patent portfolio was developed by GE Global Research and Imbera Electronics Oy (now GE Embedded Electronics Oy) as part of the GE focus in power electronics over the last decade. [link 1] They seek to provide significantly improved electrical performance (for example, reduced parasitics), increase functional density of the electronics circuits by more than a third, and can increase efficiency by over 10%.
GE Ventures has already licensed IP to TAIYO YUDEN for fabricating substrates embedded with electronic circuits in late 2014. “TAIYO YUDEN and GE are working towards the commercialization of next-generation wirebondless, embedded electronics circuits including Si-, SiC- and GaN-based wirebondless embedded electronics circuits with the technology and the IP provided by GE Ventures. “[link 2]
GE Ventures has also licensed SHINKO ELECTRONICS their advanced embedded packaging solution for power electronics called Power Overlay (POL) to “…industrialize the packaging platform and transition POL to manufacturing for GE and others.” [link 3]
For all the latest in advanced packaging, stay linked to IFTLE…