By Dr. Phil Garrou, Contributing Editor
Continuing our IFTLE look at the 2017 SEMI Euro 3D Summit.
Alistair Attard of Besi discussed “Productivity Improvements in Thermo-compression Bonding (TCB)”.
TCB allows stacking of thin devices at ultrafine pitch ansd as such is an enabling technology for 2.5D and 3DIC stacking. Currently TCB mainly addresses low value high end applications which are performance and form factor driven and have lower cost sensitivity. TCB can be used with non conductive paste, capillary underfill or non conductive films.
– Not well suited for 3D integration (dispensing at each stack layer, NCP bleed, etc.)
– Challenging process for thin dice (< 50μm) due to NCP climbing to the top of the die
– Underfill flow issues for high density fine-pitch bump arrays
– Risk of NCP entrapment in the solder joints
– No issues with adhesive bleed, adhesive entrapment, thin die handling, tool contamination
– Mature CUFs are available
– Proven process for HVM of memory stacks
BUT – Longer process times due to increased process control and solder solidification
– solder joints are not protected until the underfill step – greater risk of joint cracks
– NCF solves some issues of NCP & CUF, but it is still challenging
– Ideal process for thin die & 3D applications
– Reduced die stress due to presence of NCF (good for ULK)
– Shorter process times and collective bonding strategies enable higher UPH
– NCF voiding needs to be controlled
– NCF not yet a mature process
When compared to flip chip mass reflow, TCB is ~ 2X more expensive and is at least 5X slower. In order to be used in larger applications, these issues must be improved upon.
Productivity is increased by reducing the overall TC process time by either of the two approaches shown below (being called Vertical Collective Bonding or VCB):
Besi claims that VCB (gang bond in press) will reduce COO > 5X.
VCB bond profile needs to be optimized (Force, Temp, Timing)
– to get good NCF flow before solder reflow
– to minimize NCF voiding
– to get good soldering at all die levels
Dave Butler of SPTS (now Orbotech) discussed “Plasma Dicing is Becoming Mainstream”.
Conventional dicing includes the following techniques:
Plasma dicing, being offered by SPTS and others uses the same plasma source as DRIE, with the following reported advantages:
– Clean, chemically etched scallops
– Active cooling to prevent wafer heating
– Increased die strength
– Yield improvement –no cracking or chipping with plasma dicing
– Advantage for thinner wafers (≤50μm)
– Narrow lanes (<10μm) increase usable Si area
– Crack stop areas can be eliminated
– Parallel process
– High Si etch rates –even with more lanes for smaller die
– Option to use cluster platforms
SPTS reports plasma dicing gives ~ 2X die strength vs typical dice after grind techniques.
Reinhard Windemuth of Panasonic also presented info on “Advanced Plasma Dicing”. Pointing out the same advantages as SPTS, Panasonic reports ~ 20% increase in 0.5mm chips from an 200mm wafer due to the reduction in the size of the dicing streets as well as the near elimination of chipping and damage layers as shown below.
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