Insights From Leading Edge



IFTLE 331 IMAPS DPC Part 3: K&S Describes InFO Process Flow

By Dr. Phil Garrou, Contributing Editor

As one might expect, there were quite a number of fan-out packaging presentations at the recent IMAPS Device Packaging Conference and the next few IFTLE will examine some of those presentations.

K&S

Tom Strothmann of K&S discussed “Speed and Accuracy Optimization for Fan Out Die Placement”. Die placement accuracy in conjunction with die shift from the reconstitution process must accommodate the design rules for RDL via size, passivation opening size and pad pitch for the intended devices.

– die placement speed is directly related to cost and the highest UPH is preferred. Typically 10K UPH at 3-5um accuracy. Multi head placement has potential to place 12K UPH with accuracy of 7-10um.

– Accuracy is directly related to yield and the subsequent cost for advanced products

– > 98% yield is required for each RDL layer since compounding yield loss from multiple RDL layers rapidly erodes margins ($$). Thus a lower RDL count is better.

Panel Processing (or as we called it in the late 1990s “Large Area Processing”)

– still remains > 2 years out

– many versions still in development, panel size has not been standardized, equipment suppliers still have moving target

– panel line cost estimated at $100MM

– high speed placement required for lower costs

– panel warpage is still a problem

– die shift occurs as mold cmpd cures

– plating uniformity difficult on large rectangular panels

“High Density fan out will remain on round format for the foreseeable future”

InFO Process Flow

Of great interest was Strothmann’s discussion of the InFO process flow. IFTLE has reprduced the slides below:

K&S 1

K&S 2

Yole Developpement

Jerome Azemar of Yole discussed fan out packaging market trends. Of interest was the following chart showing various applications vs general requirements for I/O and package size ranging from the small, low IO Codec for WiFi to large, high I/O FPGA’s.

yole 1

Fan out technical challenges are described in the slide below including warpage, die topography, failure to planarize chips with mold compound resulting in RDL distortion, die shift during mold cmpd cure and solder joint issues for large packages.

yole 2

 

Yole reports 2016 fan out packaging revenues at $492MM with SCP / JCET holding 37% market share. TSMC is close behind with 35% share based on their one client Apple.

Yole 3

 

For all the latest in advanced packaging, stay linked to IFTLE…

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