By Dr. Phil Garrou, Contributing Editor
Finishing up our look at the IMAPS Device Packaging Conference with presentations by Amkor, Global Foundries and Huan Tien (FCT) on their FOWLP technologies.
With reported revenue of $972MM, Huan Tian is ranked #6 among global OSATS. They bought FCI in Phoenix in the fall of 2014. For you younger readers, Flip Chip Technology was a JV of Delco and K&S where Pete Elenius, Tom Strothmann and a host of others developed the bumping technology used today in most of the OSATS and foundries globally. They also invented and commercialized the first fan in WLP. For a review of where things stood in 2000 try this excellent review [“Wafer level chip scale packaging (WL-CSP): an overview” IEEE Transactions on Advanced Packaging ( Volume: 23, Issue: 2, May 2000 http://ieeexplore.ieee.org/abstract/document/846634/]
They have now developed an embedded silicon fan out technology as shown below.
Instead of mold compound, silicon is used as the carrier with KGD embedded and bonded in the wafer cavities. The micro gap between the die and cavity ( ~ 35um) is filled with polymer. Cavities are formed by Bosch etching and are generally ~ 100um deep.
– lower warpage – higher density RDL capability
– larger CTE miss match to the motherboard
– parts passed all standard reliability tests.
A roadmap for their embedded silicon fan out (eSiFO) is shown below.
Suresh Jayaraman discussed “silicon wafer integrated fan out technology”. Amkor sees a migration from Flip chip and fan in packaging to FOWLP as shown below.
Key drivers in the High Perform Computing (HPC) and Mobile markets are shown below. They project that eventually the high density FOWLP segment will be > 70% of the total fan out market.
Below is their roadmap for high density an out evolution.
Gaurav Sharma discussed “development of fan out package platform for high performance and Rf Applications”.
Suggested benefits for Rf Performance are shown below:
They also shared their roadmap for introduction of high density fan out technology
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