Insights From Leading Edge

Monthly Archives: July 2017

IFTLE 343 ECTC 3: Materials and Processes: Tohoku, Hotachi Chem, Samsung

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2017 ECTC.

Tohoku Univ – Low CTE Underfill

Kino and coworkers at Tohoku Univ presented their data on the “Remarkable suppression of local stress in 3DIC by MnN based filler with large negative CTE”.

Generally, CTE of the underfill material is larger than that of metal microbumps. This CTE mismatch induces local bending stress in thinned IC chips, as shown in Fig. 2 below. Such local bending stress would affect transistor performance in thinned IC chips. Kino found that they could suppress the local bending stress by decreasing the CTE difference between the underfill material and the microbumps.

tohoku 1

In general, silica, is usually used in underfill material to reduce the CTE of underfill material. A high concentration of filler is required to reduce CTE as low as metal microbumps. However, it is difficult to use the conventional filler for 3D IC with fine pitch microbumps since a high concentration of filler in underfill material increases the viscosity. They propose to use negative-CTE material as the underfill filler to suppress the local bending stress. They used manganese nitride-based material which has large negative-CTE of -45 ppm/K at the temperature from 65 to 100°C. Results indicate that negative-CTE filler can suppress the thinned Si chip bending more than 50% compared with SiO2 filler. 

Hitachi Chemical – Expanding Film for WLP Sidewall Protection

Honda and co-workers from Hitachi Chemical discussed “Expanding film and process for high efficiency 5 sides protection and FO-WLP fabrication.”

WLP is well suited to mobile devices which require small, thin and light bodies. Fan in WLP (FIWLP) is fabricated by building up redistribution dielectric and metal layer on device wafer and attaching ball, and then it is diced to singulated packages. Device semiconductor die sides are exposed in such a FIWLP. The FIWLP fabrication process needs a wide die gap between die for molding compound and to dice, while leaving the molding compound on the die side wall for the protection.

To get the greater productivity and enhance the usage of the device area in the wafer, an expandable film and a novel process have been developedas shown below in fig 2. The film / process can also be applied to a die first type FO-WLP fabrication. Elimination of the die re-placement step can make the FO-WLP fabrication process simpler and less costly.

hitachi 1

The 5 sides protection fabrication process is composed of 7 steps as illustrated in Fig. 2. The

expanding film with diced-wafer was put on the expander and the film expanded. After that the film is fixed to the grip ring , the film is cut out along the outer rim of the ring. After the singulated dice were transferred to the carrier with keeping the expanded die gap, the grip ring was removed. Then the expanding film was removed from the carrier. After over-molding, the molded wafer was singulated by dicing and 5 side protected packages were obtained.

The stress-strain curve of the film was optimized so that the die gap becomes large. Moreover, the die gap was able to be controlled from 0.5 mm to 3.5 mm. In the case of 1.5 mm die gap after expansion, the standard deviation was about 0.05 mm. Furthermore, the film was applicable to die sizes 1 mm × 1 mm, 5 mm × 5 mm and 10 mm × 10 mm.

Samsung – Compression Molding Encapsulants for FOWLP

Kwon and co-workers discussed “Compression molding encapsulants for wafer-level embedded active devices”. Challenges that FOWLP packaging technology is confronted with include wafer warpage, die shift/protrusion, and board level reliability. A solution to wafer warpage is considered crucial for successful subsequent wafer processing.

They propose to use a bilayer test structure with silicon wafer and epoxy molding compound as a standardized evaluation vehicle. Each layer is 300 μm thick. To further standardize testing, the molding conditions are fixed at 135 °C x 600 sec with a post mold cure of 150°C x 2 hrs. By standardizing the test vehicle and processing conditions, warpage behavior between mold compounds can be directly compared, and any observed differences are solely caused by the EMC.

Various parameters influencing wafer warpage were screened by the simulated calculation. Among all these parameters, Young’s modulus, CTE, and Tg have a significant effect on the controlling warpage. Generally, wafer warpage is reduced by lowering the Young’s modulus and CTE, and increasing the Tg. Although concurrent optimization of Young’s modulus, CTE, and Tg of a mold compound’s properties is very difficult because of tradeoffs for modifying each component, they developed new compression molding compounds with both low Young’s modulus and CTE, with relatively high Tg.

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 342 2017 ECTC part 2: Chip Embedding at Infineon; UCLA SuperCHIPS

By Dr. Phil Garrou, Contributing Editor

So, before we start updating on the latest technologies at 2017 ECTC a quick update on granddaughter Hannah. Long-time readers of IFTLE may recall her early pic from Halloween 2010…

hannah

I know this isn’t a sports blog, but be patient with the proud grandpa. This spring, as she approached her 13th birthday and decided to start running track in Jr High. She quickly performed to the point of taking over school records, but really that’s just a little Jr High in Houston the 5th largest city in the USA.

hannah 2

She soon got a call from Track Houston. For those of you who understand USA sports, consider this one of the USAs best AAU track teams. Historically, Houston has won 40 AAU National Junior Olympic championships with Track Houston winning 16 of those. This IS the big time for runners. You can read about them here [link].

Hannah made the 13/14 yr old team and started running against real competition around Easter in the 100m and 400m events. They say a picture is worth a thousand words, so I will leave you with this link to a 24 second YouTube video someone loaded of one of her best races. That’s her in lane 7. If I recall correctly this was run at the Rice Univ track in Houston.

For a guy who grew up playing stickball in the streets of Hell’s Kitchen, all I can say is “You’ve come a long way baby…” 

CHIP Embedding at Infineon

As we said in IFTLE 236 Embedded Packaging refers to many different concepts, IP, manufacturing infrastructures and related technologies. The two main categories of embedded packages are (1) those based on a molded wafer infrastructure such as FOWLP and (2) those based on a PWB/PCB laminate panel infrastructure.

For chip embedding in laminate, known good ICs are picked and placed on top of an organic layer of Printed circuit board and subsequent layers are laminated on top. Regular PCB manufacturing operations then take place on the panel containing the embedded ICs.

Embedding chips into laminate is a technology that has not quite caught on yet although recent announcements like ASE and TDK’s 2015 agreement for a JV (ASE Embedded Electronics Inc.), based in Kaohsiung, to manufacture IC embedded substrates using TDK’s SESUB (Semiconductor Embedded Substrate) technology are making it look much more commercially likely[link]. SESUB is a high-end substrate technology where thinned semiconductor chips are embedded in laminate substrate with copper interconnection down to 20µm minimum L/S.

At the recent ECTC in Orlando Infineon Regensburg reported on “Laminate Chip Embedding Technology – Impact of Materials Choice and Processing for very Thin Die Packaging”. The laminate embedding process consists of elements from conventional packaging technology followed by PCB process steps and dedicated chip embedding process steps. The process flow shown below is a chips first embedding technology.

Infineon 1

The process starts with die attach on a structured or unstructured copper leadframe. After die attach the copper lead frame is roughened to ensure adhesion of the laminate to the leadframe. Any process induced reduction of copper thickness must be compensated for by providing sufficient layer thickness allowance. Die positions are measured before the lamination process ( die shift compensation), leadframe strips are formed into a panel, laminated with pregreg and terminated with roughened copper sheet . Vias are defined by structuring the outer copper foils (drilling or photolith) . The via filling process consists of > 10 wet chemical process steps (desmear, activation, plating etc.).

Both unfilled resin coated copper (RCC) and highly filled prepreg were tested as laminate. Temp cycling (-55 to 150C) and HTT (150 C) show degredation of the RCC built structures, due both to cracking at the RDL corners and high leakage current.

SuperCHIPS at UCLA

For previous discussions of this technology see IFTLE 301 “Are Silicon Circuit Boards in our Future?”

In their latest presentation at ECTC, “Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme” Subu Iyer and his group at UCLA describe the performance and power benefits of their fine pitch integration scheme on a Silicon Interconnect Fabric (Si IF). They propose a Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet (chiplet) to interconnect fabric assembly. They show dramatic improvements in bandwidth, latency, and power are achievable through such a integration scheme where small chiplets (1-25 mm2) are attached to a rigid Silicon Interconnect Fabric (Si-IF) at fine interconnect pitch (2-10 µm) and short inter-die distance (50-500 µm) using solderless metal-to-metal thermal compression bonding (TCB).

With fine interconnect pitches (<10 µm), their scheme reportedly can achieve > 5-25x improvement in data bandwidth. This can improve system performance (>20x) when compared to PCB-style integration and may even approach single die SoC metrics in some cases. Furthermore they claim the protocol is simple and non-proprietary. They apply the scheme to heterogeneous system integration using a chiplet based assembly method and show significant reduction in design and validation cost.

ucla 1

They see the technology as offering a platform for system scaling. The technology aims at elimination of the use of solder by direct metal-to-metal thermal compression bonding between metal pillars on substrate, to metal pads on the chiplets. This allows them to scale down the interconnect pitch down to 2 -10 μm as the solder extrusion is no longer a limitation. They also remove the packaging of individual chiplets and place the dies directly on the Si IF with inter-dielet spacing of less than 100 μm. Thus, their data links can be much shorter (i.e. 50- 500 μm).

Analysis were done for 2 μm and 10 μm interconnect pitch with pillar diameter being half the pitch and trace width of 1 μm. SuperCHIPS provided a protocol based on fine pitch fine integration of system where the inter-dielet spacing is ~10-20x smaller than the conventional packaged systems on PCB. The fine pitch interconnects provide ~15-80x more number of I/O pins compared to BGA interconnects and ~2- 10x more compared to copper micro-bumps. Table III is presented to show comparison of SuperCHIPS vs conventional packaging:

ucla 2

Their design approach is to partition the system into chiplets that can be heterogeneously integrated on the Si-IF. This chiplet assembly approach allows them to choose heterogeneous chiplets from different technologies, nodes and materials leading to a high probability of chiplet and IP reuse.

For all the latest on Advanced Packaging, stay linked to IFTLE…