Insights From Leading Edge



IFTLE 342 2017 ECTC part 2: Chip Embedding at Infineon; UCLA SuperCHIPS

By Dr. Phil Garrou, Contributing Editor

So, before we start updating on the latest technologies at 2017 ECTC a quick update on granddaughter Hannah. Long-time readers of IFTLE may recall her early pic from Halloween 2010…

hannah

I know this isn’t a sports blog, but be patient with the proud grandpa. This spring, as she approached her 13th birthday and decided to start running track in Jr High. She quickly performed to the point of taking over school records, but really that’s just a little Jr High in Houston the 5th largest city in the USA.

hannah 2

She soon got a call from Track Houston. For those of you who understand USA sports, consider this one of the USAs best AAU track teams. Historically, Houston has won 40 AAU National Junior Olympic championships with Track Houston winning 16 of those. This IS the big time for runners. You can read about them here [link].

Hannah made the 13/14 yr old team and started running against real competition around Easter in the 100m and 400m events. They say a picture is worth a thousand words, so I will leave you with this link to a 24 second YouTube video someone loaded of one of her best races. That’s her in lane 7. If I recall correctly this was run at the Rice Univ track in Houston.

For a guy who grew up playing stickball in the streets of Hell’s Kitchen, all I can say is “You’ve come a long way baby…” 

CHIP Embedding at Infineon

As we said in IFTLE 236 Embedded Packaging refers to many different concepts, IP, manufacturing infrastructures and related technologies. The two main categories of embedded packages are (1) those based on a molded wafer infrastructure such as FOWLP and (2) those based on a PWB/PCB laminate panel infrastructure.

For chip embedding in laminate, known good ICs are picked and placed on top of an organic layer of Printed circuit board and subsequent layers are laminated on top. Regular PCB manufacturing operations then take place on the panel containing the embedded ICs.

Embedding chips into laminate is a technology that has not quite caught on yet although recent announcements like ASE and TDK’s 2015 agreement for a JV (ASE Embedded Electronics Inc.), based in Kaohsiung, to manufacture IC embedded substrates using TDK’s SESUB (Semiconductor Embedded Substrate) technology are making it look much more commercially likely[link]. SESUB is a high-end substrate technology where thinned semiconductor chips are embedded in laminate substrate with copper interconnection down to 20µm minimum L/S.

At the recent ECTC in Orlando Infineon Regensburg reported on “Laminate Chip Embedding Technology – Impact of Materials Choice and Processing for very Thin Die Packaging”. The laminate embedding process consists of elements from conventional packaging technology followed by PCB process steps and dedicated chip embedding process steps. The process flow shown below is a chips first embedding technology.

Infineon 1

The process starts with die attach on a structured or unstructured copper leadframe. After die attach the copper lead frame is roughened to ensure adhesion of the laminate to the leadframe. Any process induced reduction of copper thickness must be compensated for by providing sufficient layer thickness allowance. Die positions are measured before the lamination process ( die shift compensation), leadframe strips are formed into a panel, laminated with pregreg and terminated with roughened copper sheet . Vias are defined by structuring the outer copper foils (drilling or photolith) . The via filling process consists of > 10 wet chemical process steps (desmear, activation, plating etc.).

Both unfilled resin coated copper (RCC) and highly filled prepreg were tested as laminate. Temp cycling (-55 to 150C) and HTT (150 C) show degredation of the RCC built structures, due both to cracking at the RDL corners and high leakage current.

SuperCHIPS at UCLA

For previous discussions of this technology see IFTLE 301 “Are Silicon Circuit Boards in our Future?”

In their latest presentation at ECTC, “Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme” Subu Iyer and his group at UCLA describe the performance and power benefits of their fine pitch integration scheme on a Silicon Interconnect Fabric (Si IF). They propose a Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet (chiplet) to interconnect fabric assembly. They show dramatic improvements in bandwidth, latency, and power are achievable through such a integration scheme where small chiplets (1-25 mm2) are attached to a rigid Silicon Interconnect Fabric (Si-IF) at fine interconnect pitch (2-10 µm) and short inter-die distance (50-500 µm) using solderless metal-to-metal thermal compression bonding (TCB).

With fine interconnect pitches (<10 µm), their scheme reportedly can achieve > 5-25x improvement in data bandwidth. This can improve system performance (>20x) when compared to PCB-style integration and may even approach single die SoC metrics in some cases. Furthermore they claim the protocol is simple and non-proprietary. They apply the scheme to heterogeneous system integration using a chiplet based assembly method and show significant reduction in design and validation cost.

ucla 1

They see the technology as offering a platform for system scaling. The technology aims at elimination of the use of solder by direct metal-to-metal thermal compression bonding between metal pillars on substrate, to metal pads on the chiplets. This allows them to scale down the interconnect pitch down to 2 -10 μm as the solder extrusion is no longer a limitation. They also remove the packaging of individual chiplets and place the dies directly on the Si IF with inter-dielet spacing of less than 100 μm. Thus, their data links can be much shorter (i.e. 50- 500 μm).

Analysis were done for 2 μm and 10 μm interconnect pitch with pillar diameter being half the pitch and trace width of 1 μm. SuperCHIPS provided a protocol based on fine pitch fine integration of system where the inter-dielet spacing is ~10-20x smaller than the conventional packaged systems on PCB. The fine pitch interconnects provide ~15-80x more number of I/O pins compared to BGA interconnects and ~2- 10x more compared to copper micro-bumps. Table III is presented to show comparison of SuperCHIPS vs conventional packaging:

ucla 2

Their design approach is to partition the system into chiplets that can be heterogeneously integrated on the Si-IF. This chiplet assembly approach allows them to choose heterogeneous chiplets from different technologies, nodes and materials leading to a high probability of chiplet and IP reuse.

For all the latest on Advanced Packaging, stay linked to IFTLE…

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