By Dr. Phil Garrou, Contributing Editor
Will IoT require “dirt cheap” packaging?
Those of you following IFTLE’s position on IoT know that while I certainly see a future where the wireless collection of data proliferates, I see this, in general, for extreme low cost packaging solutions, certainly not, as some have said in the past, an IoT using 2.5/3D solutions.
In seeming agreement with that conclusion, Rick Merritt of EE Times describing the recent ARMTechCon reports that the panel discussion on “Breakthrough Technologies enabling the future of IoT” concluded that the future of IOT could depend on a chip that sells for less than 50 cents, that SoCs will need new kinds of memories, connectivity and sensors to scale to dimensions the IoT will demand, and that the path to get there is still unclear. [link]
He reports that SRAM and flash memories, Bluetooth interfaces and sensors consume too much power to serve volume IoT nodes in 2027 where ideally, ARM reports, an end node SoC would consume just 10 microwatts/MHz and send and transmit data on a radio drawing only 1 or 2 mW. In terms of transmission, radios need to ultimately scale to power levels of a tenth the power of today’s Bluetooth Low Energy which perhaps will require a new radio maybe on new frequency bands which might take a 10-year effort to execute. Sensors will also need to explore new materials and design techniques to lower power, shrink size and add features. Sensors will need heterogeneous integration packaging technologies to integrate them into modules. “ … so the package becomes the sensor with silicon inside it”. Bottom line seems to be, as we have stated before, that the packaging solutions for IoT will have to be “dirt cheap”
SEMICON Taiwan continued…
In his presentation on “New Materials for Fan-out WLP,” Tony Flaim of Brewer proposed an interesting new fan out concept where cavities are laser drilled into a laminated sheet, chips are inserted face up into the cavities and thin film RDL is created over the chips as shown below.
IFTLE is not a big fan of making technology decisions based on cost modeling. My past experience has shown that he cost models that I have used are generally very accurate when all the inputs are well known and not very accurate when the inputs are being “guestimated”. Having said that, I do like the slide presented by Chet Palesko of SavanSys Solutions on the general comparison of embedded die vs FOWLP vs TSV solutions shown below…
ITRI always gives us a nice update on activities in Taiwan. Below we see that Taiwan foundry services currently account for 70% of the world wide market and the Taiwanese IC packaging and test services account for 55% of the world wide SATS market.
Dave McCann of GF showed a nice process flow for their 2.5D production where the interposer fab, logic fab, memory fab and OSATS must work together to deliver the finished product.
Next week, we will begin our look at IMAPS 2017. For all the latest in advanced packaging, stay linked to IFTLE…