Insights From Leading Edge



IFTLE 370 3D-ASIP Part 3: Bonding and Assembly in HBM Memory Stacks

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 14th annual 3DASIP Conference.

K&S

Tom Strothmann of K&S discussed the requirements for HBM Memory Stacking. High Bandwidth Memory (HBM 1,2) are currently assembled using C2W compression bonding. Production is mostly done by memory suppliers as opposed to OSATS. HBM 3 is projected for 2019.

K&S 1

There are two prominent stacked die process flows:

    • TC-CUF (Thermocompression with Capillary Underfill)
      • Die by die stacked using TCB
      • Die stack tacked followed by mass reflow
    • TC-NCF (Thermocompression with Non-Conductive Film)
      • Stacked die by die using TCB
      • Die stack tacked followed by Collective Bond
      • Die stack tacked followed by Gang Bond

Cost reduction has focused on units/hr for the TCB process:

    • Bondhead temperature ramp speed
    • Target and die material handling systems
    • Number of bondheads and accuracy requirements

Tacking has the potential to move machine UPH from 1700 to 3500 for a 4 die stacked process using NCF if a separate gang process is used.

K&S 3

 

TSV Die Stress and Warpage

  • Silicon thinned to 50 microns during the via reveal process then has backside dielectrics and UBM applied
  • Imbalanced stress resulting from the dielectrics, metals and pillars on the front of the wafer as compared to the back of the wafer causes warpage in the thinned silicon wafer
  • Stress remains after dicing, resulting in die bowing that can be as much as 40um in a 9x9mm die

TCB with CUF Process

  • TC-CUF processes have been used for stacked die production in HVM. Flux dip before placement followed by capillary underfill is a mature process.
  • Typically lower throughput because the flux dip must be done below 100ºC to avoid premature activation of the flux. UPH >1000 is still possible during bonding with a dual head machine.
  • TC-CUF die stacks have a narrow process window due to thin die warpage. Single die can be held flat during the bonding process , the next die in the stack does not. Heat is conducted through the thin silicon and Cu pillars into the die below, causng solder remelt and relaxation to original warped shape resulting in BLT variation. Since the top die is still held flat, this can create inconsistent bondline thickness throughout the stack.

TCB with NCF (non conductive film)

  • NCF has the benefit of locking the BLT during the bonding process to enable a “flat die” process and more consistent bond lines
  • TCB process can be optimized independent of die stack position
  • Potential to remelt a lower die and change BLT is removed, enabling better process capability
  • But…high forces may be required for bonding some layers based on die size and pillar count

As shown below the thickness of the NCF must be exact or the interface will suffer from particle entrapment or voiding.

K&S 2

Strothmann also offered the following opinions on alternative bonding approaches:

  • Cu-Cu bonding is an area of active development work but is less likely to be applied to memory stacking in the near future
  • Direct (hybrid) bonding of chip to wafer is unlikely for memory stacking

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One thought on “IFTLE 370 3D-ASIP Part 3: Bonding and Assembly in HBM Memory Stacks

  1. Dr, Dev Gupta

    ” Strothmann also offered the following opinions :

    … Direct (hybrid) bonding of chip to wafer is unlikely for memory stacking ”

    Why ?

    Reply

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