By Dr. Phil Garrou, Contributing Editor
Boon Chye Ooi , Sr VP of Operations for Broadcom spoke at the IEEE ECTC luncheon addressing “Packaging advancements to enable artificial intelligence (AI), autonomous cars and wearables in the near future: cost and implications to supply chains.”
Ooi leads the global operations organization which is responsible for worldwide manufacturing including foundry and package engineering, outsourcing, procurement and logistics, planning and quality programs. Ooi indicated that he saw packaging as having played a vital role in enabling semiconductors to penetrate new application frontiers such as artificial intelligence (AI), autonomous cars and wearables, but for their ubiquitous deployment, the packaging community must make these technologies cost competitive and multi sourced.
He had 3 questions for the supply chain:
- Is the OSAT/Foundry willing to invest fab like yield tools?
- Will there be sufficient capacity and reliability of supply?
- How will cost excursions and miss-processing be handled by the infrastructure?
His call to action for the supply chain of 2022 included the following points:
- Upgrade assembly yield management to Fab level
- Develop u-bump probe and test technologies for improved yield
- Develop substrates for low loss mm wave channels on large packages
- Develop low cost thermal solutions to reduce system cost
- Develop multiple suppliers for silicon content, packaging raw material, substrate and assembly
Specific technical challenges included the following:
|Data rate||112 Gbps||· channel insertion loss and return loss
· power integrity
|Package Body size||> 90 x 90mm||· package warpage
· board level reliability
· socket cost and performance penalty
|2.5D Integration||More and larger dies||· interposer reticle size
· assembly challenges
· more memory bandwidth
|u-bump pitch||< 30um||· assembly challenges
· routing challenges
|Power dissipation||>500W||· thermal interface materials
· heatsink solutions
Rumors from San Diego
With 1750 attendees present there were sure to be numerous rumors making the rounds at ECTC. In time some will clearly turn out to be true and some will not, but all of them are certainly interesting enough to consider.
One rumor I can confirm is that Rao Tummala, unquestioned “Father of Microelectronics Packaging” will be retiring imminently. Tummala, now in his mid 70’s, has informed Ga Tech and his PRC that a successor should be located. He will be helping his replacement for a few years to ensure a smooth transition but he is looking forward to relaxing, spending more family time and playing more golf. It certainly will be interesting to see who Ga Tech finds to fill his shoes.
As I have detailed several times in IFTLE, BT (before Tummala) packaging was an after thought carried out by failed front end engineers. In 1989 Tummala, while still at IBM, joined Gene Rymaszewski editing the first Microelectronic Packaging Handbook categorizing this technology for the first time. In 1993 Tummala left IBM to set up an NSF PRC (packaging research enter) at Georgia Tech to explore and develop packaging concepts and, just as importantly, educate highly-interdisciplinary students in this concept. This NSF funding was supplemented by more than 50 U.S. companies and the State of Georgia. 20 new faculty were recruited with expertise in every electronics area. The 1st of a kind cleanroom pilot line for package, assembly and reliability was built at a cost of $47M. In the intervening years more than 400 PhD, 470 MS and 340 BS engineers all specializing in packaging have graduated from this program and populated the electronics companies around the world. In 1997 the Packaging handbook was rewritten in 3 volumes and more than 2000 pages. The chapter author list is a who’s who in the field of packaging. I am proud to have been part of that endeavor. Below is a photo we took in Slovenia together 21 years ago in 1997.
In 2001, Rao produced what I consider the first undergrad / grad packaging text “Fundamentals of Microsystem Packaging,” which has been used to teach electronics packaging in many of our universities. He and I co-wrote the chapter on wafer level packaging, a new concept at that time. My point in reciting all this is to simply backup my statement that these will be very large shoes to fill. It will be interesting to see who will fill them.
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