Author Archives: insights-from-leading-edge

IFTLE 152 2013 IMAPS Device Packaging Conference part 2

Continuing with our coverage of the March IMAPS DPC.

TI

In his keynote presentation on semiconductor packaging trends Devan Iyer of TI showed  a great chart on package shrinkage through the years. We have moved from the 1.75mm SOIC to the picostar 2G at 0.075mm which they claim to be the thinnest package available for portable products and can be buried into PCB layers . 

 

 Iyer  also listed the following packaging challenges for materials and assembly.

 
APSTL
Dev  Gupta of APSTL  examined  “Stacked package with improved bandwidth and power efficiency” . His conclusions are  based on the assumption that 2.5/3D technology is still immature and high cost and not ready for adoption in consumer products like smart phones. He is a proponent of what he calls “super PoP” packages.
He points to the recent presentations by JEDEC which indicated that TSV based wide IO would be an option for 2015 but would find strong competition in LPDDR4. { For further discussion of this issue see IFTLE 134,  SEMI 3D European Summit – Is the Wide IO Driver Dead ?” ]
 
Gupta claims that the issues for Pop arise from increased power loss due to parasitics in the package and that this can be cured by inserting “signal conditioning chips “ (442)
???
 
Nanium
Nanium announced that they were installing  30mm WL fan in technology (Spheron PBO technology from Flip Chip Int) to compliment their WL fan out technology already in place.
Corning
Corning discussed their 3D carrier glass substrates used in the wafer thinning process. 
They supply glass carriers for the 3M temp bond / debond process. Their fusion glass process results in surfaces with RMS 0.3nm; Ra 0.2 nm and Z range 4.2nm which is better than lapped and polished glass.
???
 
200 & 300 mm wafers cut out of a sheet. 450 will not be a problem and panels are ready when the industry becomes ready to use them.
They are using alumino-silicate glass (SGW3) to match CTE od Si from 0 – 300 C.  This CTE match keeps warpage very low. Corning pointed out that measuring TTV on these wafers is difficult and that reports in the literature of 1 um TTV are sometimes as far off as 5 um.
Recycling glass wafers depends on all process perameters, but in general they envision  15 recycles as doable.
For all the latest in 3DIC and advanced packaging stay linked to IFTLE………….
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IFTLE 151 2013 IMAPS Device Packaging Conf part 1 – Amkor

I’ll be interspersing reports from DPC with ECTC and ICEP reports so pay attention as to where the material over the summer is coming from. In addition I will be covering ConFab and Semicon West so there will be a lot of information coming your way.

The IMAPS DPC , Proceedings and the Literature Search Problem

We are finally getting around to taking a look at the March IMAPS  Device Pkging Conference. Actually it is officially listed as a workshop, which to IFTLE is inappropriate since it runs 3 parallel sessions for 2 ½ days and has a very large exhibit tied to it. It seems the driving force to not change is that SOME don’t want to write up their papers for a proceedings which would be required if it were officially a conference. These are probably the same authors who don’t ever hand in, or take 2+ months to turn in , their slides. When I was general chair I tried twice to require a proceedings and was voted down twice, so don’t blame me !

In the end its all about literature searching. We all have become so accustomed to using Google scholar that if it doesn’t show up there we just ignore it. If I don’t have a copy of a specific proceedings and its papers don’t show up in Google Scholar basically the material does not exist. Sure I can go to each societies web page, and become a member and then search their archives but how many of us do ? Right now that means we all reference quite a bit of literature from IEEE explore because Google indexes it and our companies / institutions pay to access it.

Other societies need to make sure their material is archival and searchable otherwise after a few years it is really lost. I know IMAPS specifically is working on this problem and I hope all the other societies are too.

IMAPS DPC – AMKOR

Lets start our DPC look with presentations from Amkor. Being close by in AZ, Amkor always brings a strong contingent to the DPC.

Amkor discussed their thermo compression non conductive paste process for formation of copper pillar bumps. Copper pillar bumping achieves better electrical performance as well as smaller packages with lower standoff heights. It is also expected to lower costs by reducing substrate layer counts. The bump process flow is shown below:

 
The assembly process for thermocompression bonding with non conductive paste (TCNCP) is shown below. Key to the assembly process is control of the peak heating temp and the heating time.
 
 
 


Amkor also discussed mold shrinkage and die stress effects on FC molded BGAs.
 
FCBGA can be molded using either mold compound or molded underfill. Schematic of molding is sown below. Increased shrinkage increases both  tensile and shear stresses.
Stresses are concentrated in the mold/ die interface in the mid section of the die.  The rubber insert used to protect the die surface creates a grove in the top of the molded surface. This grove controls the stress on the overall package and this package warpage.
 

Kelly of Amkor  discussed “Assembly challenges for 2.5D”. Their latest roadmap now shows memory + logic modules pushed back to the 2014 – 2015 timeframe.

 
Their TSV manufacturing experience base is based on :

 
High performance products now look like they are coming in 2014 – 2015 with smart phone % tablets coming in 2015+ as prices come down
Amkor has been engaged with > 10 top tier customers with > 20K parts built. There has been a  large package  focus (> 40mm) . While the slides showed interposers from 3 different “foundries” upon questioning they admitted that TSMC is delivering and the other two (Global and UMC) are close.
Process technology
- Their copper pillar bump process is on 40-45um for most customers roadmaps.
- for die joining  mass reflow is preferred but warpage must be well under control. TC bonding is an option for higher die warpage.  TCNCP can be used for small die and CUF for larger die.
- backside passivation must be mechanically stable, good adhesion to underfill and provide warpage control. In the Q&A session they indicated that they preferred inorganic backside dielectric “â??¦sometimes with a final organic cap” indicating that the “â??¦backside oxide must be incredibly mechanically robust. “
- Interposer top side to bottom side die interfaces must be flat in order to assemble.
- Need to know top side stress on incoming wafers in order to properly assemble.
- memory stacks are pretested
Comparison of 3 assembly flows is given below

 
For all the latest in 3DIC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 


IFTLE 150 ICEP Osaka part 1

The Int Symp on Electronic Packaging was held in Osaka the week of April 10th with keynote

speakers, Dr. Subramanian S. Iyer of IBM, Dr. Takeshi Uenoyama of Panasonic, and Dr. Urmi Ray of Qualcomm. General Chair was Shintao  Yamamichi of Renesas and Technical program Chair was Hitoshi Sakamoto was NEC.

 There were 180 papers and over 20 posters. Major topics were: Advanced Packaging, Substrate & Interposer, 2.5D and 3DIC Packaging, Design/Modeling/Reliability, Thermal Management, Materials and Process, Printed Electronics, N-MEMS, Optoelectronics, Power Devices, and Biomimetics. In addition, the Japan ASET consortium, Taiwan and Korea held special sessions. IFTLE will cover key presentations over the next few weeks.  

 
ASET SPECIAL SESSION

 Lets first take a look at the ASET special session. The ASET “Dream Chip” program has recently ended in Japan.


Sueoka and co-workers described their proposal for “High Precision Bonding for Fine Pitch Interconnection”. Bonding fine pitch interconnect requires consideration of the factors which degrade the alignment accuracy such as:

- thermal expansion of the machinery

- surface topologies of the chip an substrate

 The were able to bond 10um pitch bumps (see figure) using a flip chip bonder equipped with infrared alignment optics they found that they could observe alignment marks and adjust the chip position during the bonding process, even when the solder was molten. Most importantly they could eliminate the miss-alignment caused by joining non flat chips an due to thermal expansion of the tool head.

This dynamic alignment bonding scheme consists of 4 steps:

(1) pre-align for the approach of the chip to the substrate

(2) small gap align with IR light
(3) correct alignment for offsets caused by impact of the chip touching the substrate
(4) final align during the bonding while the solder is molten.

 



  Renesas and IBM Japan described “3D Package Assembly Development with the use of Dicing Tape Having NCF Layer”.

 Dicing and stacking are important technologies n 3DIC assembly. Bumps on the wafer backside make it difficult for general dicing tape to achieve both high quality dicing and pickup. For tight pitch, small bump bonding it is also difficult to inject underfill into the narrow gap between the dies.  

General dicing tape cannot burry the bumps and thus fully fix the die. This causes chipping and cracking of the die during dicing. If you increase the tapes thickness to fully burry the bumps, die pickup becomes difficult. Process flow is shown below.

 
ASET studied a new ICF tape from Nitto Denko. The tape has a NCF layer (non conductive film) on the dicing tape.  Since this NCF layer ends up staying in the gap as underfill, they call this Inner chip film or ICF (just what we need more acronyms !)  Hot lamination of the tape to the wafer will burry the backside bump. Wafer and NCF layer are diced together. The die pick up becomes easy since the required separation is between the ICF and the dicing tape adhesive.
 
 
The new process using ICF tape is shown below.
 
 

 

Hozawa and ASET co-workers at ASET described their “3D Integration Technology using Hybrid Wafer Bonding and its Electrical Characteristics”. In this study ASET examined 3D integration with vias last. Vias last was examined because it needs no modification of the front end process. The test structure and target specs are shown below.
 
 
 The process flow consists of: TSV formation; bump/contact ad formation; substrate thinning and stacking.
They examined W2W bonding and thinning after bonding as process flows.
 
Hybrid bonding was chosen where Cu-Cu and polymer – polymer bonding (they used PBO)  occur at the same interface. Hybrid bonding provides both strong metal bonding and reliable polymer underfilling simultaneously.

 
 
In the full process sequence a silicon interposer wafer and the first device wafer are bonded F2F with hybrid bonding. After backside thinning the first device wafer, TSV formation and backside bumping the second device wafer  is bonded to the stack B2F. Lastly the silicon interposer is thinned, TSV formed and bumps attached.
To achieve good CU-Cu bonding in the hybrid bonding “hydrogen radical” treatment of the Cu surface was necessary. When they tried plasma treatment it damages the PBO surface. A cross section of the interface is shown below.
 
 

Serial resistance of a 3 layer connection (2 TSV, 1 Cu-Cu bond, 1 Cu-TSV bond) is under
0.5Ω.
 For all the latest on 3DIC and advanced packaging stay linked to  IFTLEâ??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦..
 
 
 
 
 
 

 


IFTLE 149 2013 ECTC part 1

The undisputed Jewel of IC packaging conferences, the  ECTC (Electronic Component Technology Conference) took place this past week in Las Vegas with 1300+ attendees, 95 exhibitors and IFTLE in attendance.

Over 600 submitted abstracts resulted in ~300 presentations (verbal and poster) and the highest rejection rate in the industry.  Key to this years conference success were Program Chair Beth Keser from Qualcomm, General Chair Wolfgang Sauter from IBM,  and Assistant Program Chair Alan Huffman from RTI Int.

 
Beth Keser, Wolfgang Sauter and Alan Huffman from the ECTC Program Committee
John Lau Wins IEEE CPMT Field Award
Awards are an important part of this yearly conference and the pre-imminent packaging award is IEEE CPMT’s (Component, Packaging and Manufacturing Technology Society) “Field Award”  Past years winners include Rao Tummala (packaging), Yutaka Tsukada (underfilling),  Paul Totta (bumping); Herb Reichl (packaging); George Harman (wire bonding), Dimitri Grabbe (connectors) and CP Wong (polymers).
 
This years winner Is Dr. John Lau, currently a Fellow at ITRI. Best known for his extensive work in solder joint reliability, anyone who has a few packaging books on their bookshelf probably has one of Johns. One of my personal favorites is his chip on Board volume published in the 1990’s. If I am remembering correctly, John once told me that his daughter Judy designed the cover.
 
 
 
 
 
Bill Chen (ASE), CP Wong ( GaTech ), John Lau ,wife Theresa and daughter Judy Celebrate his award
Other major award winners included:
Outstanding Contribution Award – Rolf Aschenbrenner, Fraunhoffer IZM Berlin
Outstanding  Sustained Technical Contributions Award – Dongkai Shangguan, National Center for Advanced  Packaging – China
 
Exceptional Technical Achievement Award -  Yong Liu, Fairchild
Electronic Manufacturing Technology Award – Louie Huang, ASE
This years event was also loaded with  panel sessions including  Broadcom’s Sam Karikalan chairing “The role of Wafer Foundries in the Next Gen Packaging”; CPMT President Ricky Lee of Hong Kong Univ of Science and Techniology, chairing “LEDs for Solid State Lighting” ( Lester Lightbulb was seen in tears after he was informed that he was not selected to speak on this panel ); Amkor’s Lou Nichols chairing “Packaging Challenges  Across the Wireless Supply Chain” and   Fujitsu’s Yocouchi-san chairing “Low Loss Dielectrics for High Frequency and High Bandwidth”
Without question the leading theme at this years conference was once again 3DIC. I counted at least 12 sessions and numerous posters that dealt with the various components of 2.5 and 3D technology. 
3DIC Status
There were no major commercial announcements or major technology advances in 3DIC.  Presentations tended to show  slow steady movement forward for both 3D and advanced packaging in general. Over the next few weeks we will discuss this further and will take a look at some of the more interesting presentations at this years ECTC.
IFTLE also thanks Cornelia Tsang of IBM for guarding his seat during the ECTC gala celebration ! (inside joke)
For all the latest on Advanced Packaging and 3DIC stay linked to IFTLEâ??¦â??¦â??¦â??¦


 


IFTLE 148 The Future of Packaging: A Look From 50,000 Feet

There is a saying in American business that recommends if you really want to understand something you need to take a “50,000 foot look” (for those of you on the metric system, that’s 15.2 km). The logic behind this goes something like: if you’re engaged in a battle and need to know how to position your troops, better to be looking down from above than be in the midst of the battle.  Exactly where the number 50,000 comes from, I haven’t a clue. 50,000 feet is way above the clouds and certainly would not allow you to see troop movements. If I had made up the phrase, I would have said, “Let’s take a hot air balloon look” above the fray, but close enough to the ground to see what is going on.

Anyway, the IMAPS Device Packaging Proceedings have still not arrived (since March!), ditto on the April ICEP proceedings, and the ECTC is yet a week away. So, I thought we might  take  “a hot air balloon look” at our industry.


The front end drives everything


Even though you came to this blog to read about packaging, clearly understand that packaging is driven by IC fabrication (the front-end) and that will never change.

IC fabricators make their big profits on the leading edge node, not on the older, more available nodes.

New materials are introduced on the leading edge, and once these processes are locked down (qualified), they are very hard to change.  This is why equipment suppliers and materials vendors have always spent much of their hard-earned profits on trying to get qualified into the next generation node products.

The End is Coming! Soon. Maybe.

Everyone reading this blog understands the “Moore’s Law Coming to an End” arguments. Exactly when it will happen is, to me, less relevant than the fact that it is happening or has already happened for many mid-tier IC fabricators.

Some top-tier fabs / foundries will find a way to move forward past 22nm to 14nm and beyond, but the important point is that the vast majority won’t. This is not because the technology won’t be available to them, but rather because it will be too expensive. You have seen my slides on this before. Since it is very important that you understand it, I will show them to you again.


The conclusions are simple:
1. There are only a few companies with enough revenue to justify developing and building $6B+ fabs for 22nm and beyond.



2. There are very few products that have enough volume to absorb the design costs inherent to 22nm and beyond designs.




The players that can afford to move forward at this point appear to be Intel, Samsung, TSMC, GlobalFoundries, UMC and Hynix. Maybe one or two more appear through consolidation, but, in general, that’s it.  
Packaging Is Becoming More and More Importantâ??¦and valuable
In the future, product differentiation in most product lines will be achieved by the packaging used, not by the incorporation of chips of the latest node.  What we are seeing in the industry is TSMC, Samsung and maybe others making a strong move into IC packaging.
Equipment Vendors Consolidating as Customer Base Shrinks
For equipment vendors, the leading edge node customer base is shrinking, and thus you see some of them (litho, 450mm) requiring investments from the IC fabricators before putting money into future node developments.
Typical front-end equipment vendors led by Applied Materials, Lam etc. are also  acquiring  back-end equipment vendors to expand their product offerings.
Front-end equipment vendor acquisitions in back-end packaging equipment was, at first, met with skepticism by the packaging community, since front-end equipment has significantly higher margins than back-end packaging can afford. More recently, they have realized that the front-end chip fabricators are moving into the back-end packaging business and are going to their traditional equipment vendors to meet their needs.

Material Suppliers Consolidation Coming ?
It is only logical that the next round of consolidation will come from the materials suppliers.

Materials suppliers have traditionally been quite ignorant when it comes to the actual applications where their materials are to be used. Most blindly follow the roadmaps put out by the industry without really understanding them. In several instances, the low K fiasco of the late 1990s comes to mind. They followed the Pied Piper right over the cliff with many of them loosing tens of millions of dollars, trying to develop spin on polymer dielectrics that were really never going to be used.  



Materials suppliers, once again, need to be very careful when developing for the sub 22nm nodes (on chip or packaging) or for 450mm processes, because the number of companies working on these programs is likely to be significantly greater that the number of potential customers. History tells us that there will only be one or two processes / materials sets chosen by these six-ish players and the potential losses incurred here, by the materials suppliers whose solutions are not chosen, may in fact lead to the eventual consolidations that I predict.

In addition, speaking to many fabs and foundries they all appear to be attempting to minimize the number of suppliers they engage as a cost containment issue. I will not be surprised to see old qualified processes trying to replace generic materials with favored vendor equivalents.
These are not unusual outcomes; in fact, they are natural for an industry that is entering its “mature” stage, and that is certainly where we are headed.  
Hope to see many of you all in Vegas at ECTC.
For all the latest in 3DIC and advanced packaging, stay liked to IFTLE.



IFTLE 147 IME Updates 2.5D; Qualcomm Updates 2.5 / 3DIC at ICEP

IME Updates Interposer Research


In the latest issue of Future Fab Int Singapores IME updates their 2.5D through-silicon interposer (TSI) technology development [link]

GQ Lo, deputy Director Director of Research, and his 3D group point out that "3D IC…is confronting bottlenecks, such as tools for designing optimal 3D systems and thermal solutions for 3D ICs" and that "2.5D through-silicon interposer (TSI) technology is gaining momentum, both in the foundry and the outsourced semiconductor assembly and test (OSAT) universe."

They state that interposer technology provides easier fabrication, alleviates 3D thermal bottlenecks and supports the fabrication of heterogeneous integration. They demonstrate the fabrication and characterization of a 2.67 x 4.3 cm2 interposer on a 300 mm processing line. Processor + memory integration is an ideal 2.5D application since "dies can be heterogeneous (e.g., logic and memory) and can belong to different technology nodes (e.g., 28nm for logic and 40nm for memory, or 130 nm for BiCMOS chips."

The TSV (12 µm x 100 µm ) were Bosch etched into a 300mm wafer. TEOS oxide was deposited to isolate the TSV from the silicon substrate; Ti / Cu sputtered as a barrier metal and copper seed. Copper was electroplated, and overburden removed by CMP after copper anneal. Three single-damascene processes were applied to form frontside M1, via and M2 on top of the TSV.

ZoneBOND technology was used for wafer temporary bonding and de-bonding. TSV wafer was back-ground to near TSV depth, the remaining silicon substrate was etched to expose the TSV from the wafer backside and low temp dielectric films deposited and CMP’ed. Back side barrier metal and Cu seed were sputtered on the back side dielectric, and the RDL was plated up, patterned and bumped.

The cross-section of TSV and FS metal is shown below.

The electrical performance (C-V and I-V curves) of the interposer was characterized for TSV capacitance (CTSV) and leakage current after top M2 metallization and before TSV reveal.

The leakage between four TSVs with connection pad to silicon substrate (measured TSV good dies after C-V characterization) is less than 1 pA for a voltage range 0-100 V, suggesting satisfactory isolation between the TSV and the silicon substrate.

The yield of the front side M1-TSV-BS RDL chain and front side M2-via-M1-TSV-BS RDL chain were 90 percent and 85 percent, respectively.

Resistance of the TSV and backside RDL (line/space 10/10 µm) are shown below:

 

Qualcomm at ICEP

At the recent ICEP (Int Conf on Electronic Packaging) in Osaka Japan, Qualcomm’s Umi Ray presented "Architecture Trends in Mobile Industry and Impact on Packaging and Integration," updating their smartphone activities "one device many functions." They supported the Gartner projection that 5 billion smartphones will be sold between 2012 and 2016.



Ray proposed that we would be seeing 2.5 / 3D in our phones soon and showed the following roadmap, although the time axis was left vague:
The first implementation target will be wide IO memory on logic and so far, they have seen "no technical show stoppers." As we have discussed in the past, pricing remains the key challenge.


For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.

IFTLE 146 TSMC Apple Rumors; Gartner OSAT Mkt Numbers; Novati

More Taiwan rumors on TSMC / Apple relationship

 Digitimes reports that TSMC will get  100% of the application processor orders for 2014 model iPhone [link]

 Digitimes further reports that  "in order to satisfy the huge demand from Apple, TSMC has begun equipment move-in for the phase-5 facility of its 12-inch fab â??¦. Fab 14, Phase 5â??¦.[this] facility will be ready for production by the end of 2013, the sources indicated." TSMC has previously disclosed that the Fab 14, Phase 5 facility is a 20nm-capable fab, scheduled to begin volume production in early 2014.

They further report that Samsung, which produces APs for the existing iPhones, will still manufacture chips for the upcoming model scheduled to be released in the second half of 2013.

OSATS Market at $24.5B

Gartner estimates the worldwide outsourced semiconductor assembly and test services market totaled $24.5 billion in 2012.

As shown below ASE remains No. 1, with revenue of $4.4B with packaging accounting for about 80 percent of the company’s total assembly/test/materials revenue.

Amkor revenue was $2.8 billion, and  SPIL third at $2.2 billion, with 90 percent of the revenue from packaging and 10 percent from test. STATS ChipPAC is fourth with $1.7B.

Powertech Technology (PTI) at $1.4B is differentiated from the others in that the majority of its revenue comes from servicing the memory segment of the semiconductor market.

As shown below Taiwan currently controls nearly 50 percent of this market, with he next largest players, USA, Japan and Singapore far behind at about 10 percent each.

The full Gartner report can be found here [link]
Novati
Bob Patti of Tezzaron, a 3D industry leader for more than a decade recently gave a presentation explaining their acquisition of what is now called Novati. Many of you may know that this was the former Sematech Austin fab which over the years morphed, was   merged with Cyprus Semiconductor emerging as SVTC and now has been sold to Tezzaron. This is shown in the slide below.

Below is a photo of the location and a list of current capabilities


Bob indicates that their TSV connection to BEOL wiring happens  "near end of line" (reminiscent of IBM),  as shown below:
Their plan is to be a foundry for 2.5D interposers as well as 3D stacking. IFTLE will be keeping an eye on their future activities.  
For all the latest in 3DIC and advanced packaging, stay linked to IFTLE.


IFTLE 145 GPU Roadmap, IEEE 3DIC back in SF; ConFab 2013 Pkging

NVIDIA has publically updated their roadmap with the announcement of the GPU family that will follow 2014’s Maxwell family. That new family is Volta which will use stacked DRAM, which will be connected to the GPU with TSV.

NVIDIA is targeting a 1TB/sec bandwidth rate for Volta, which to put things in perspective is over 3x what GeForce GTX Titan currently achieves with its 384bit, 6Gbps/pin memory bus (288GB/sec). This would imply that Volta is shooting for something along the lines of a 1024bit bus operating at 8Gbps/pin, or possibly an even larger 2048bit bus operating at 4Gbps/pin. Volta is still years off, but this at least gives us an idea of what NVIDIA needs to achieve to hit their 1TB/sec target [link]

GPU Technology Conference in San Jose. CEO Jen-Hsun Huang was visibly anxious to unveil the company’s Volta, their upcoming GPU targeted for a 2016 release.

"Volta is going to solve one of the biggest challenges facing GPUs today, which is access to memory bandwidth," Huang told the attendees.

Move up http://i.forbesimg.com t Move down The Volta GPU will introduce stacked DRAM which will deliver 1 terabyte per second of memory bandwidth.

Below is a shot of the Volta with stacked DRAM (drawn to scale)

Huang didn’t provide a timeline for Volta’s release, but 2016 seems reasonable since  Nvidia debuts new GPU architectures every two years.
Huang said that Nvidia will be putting the stacked DRAM and the GPUs onto the same silicon substrate and inside of the same packaging before it welds that package to a peripheral card.
4th Annual IEEE 3DIC Coming to SF in October
The IEEE 3D meeting 3DIC has rotated through Germany and Japan and is back in San Francisco this October 2-4 (link). Paper submission deadline is April 30th.
3D & Packaging Lineup for SST Confab
The full description of SSTs ConFab  2013 can be found here (link)
This years packaging and 3D sessions are co-sponsored by the Component, Packaging and Manufacturing Society (CPMT) of IEEE.


For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.


IFTLE 144 Personnel Changes in Taiwan; Glass Usage in WLP

Apologies for the delay in covering the IMAPS device packaging conference this year. I normally get access to the manuscripts as I am leaving the show to insure timely coverage. This year that was not possible. IMAPS’ move of their office to the RTP NC area is causing further delays (they will soon be my neighbors), so I await the conference CD like the rest of the attendees.


Personnel Changes in Taiwan

The word from Taiwan is that Doug Yu, who has been responsible for the R&D of exploratory technologies including FEOL, BEOL and 3D IC has been refocused on just packaging, especially their CoWoS 2.5D offering.  IFTLE thinks this move shows that TSMC is serious about expanding  this business within their company.
We also hear that Ho Ming Tong currently General Manager and Chief R&D Officer at ASE, who has been a strong supporter of 3DIC, and is actually credited with coining the phrase 2.5D,  is moving further up the corporate ladder at ASE.
Congrats to both gentlemen!

 The Current and Coming Use of Glass in WLP
 We have recently discussed Asahi Glass entering the 2.5D glass interposer market [see IFTLE 141, "100GB Wide IO memory; AGC GlassInterposers; Nvidia talks stacked memory"] and the general use of glass interposers for 2.5D fabrication [ see IFTLE 54 ,"2011 ECTC and GlassInterposers"

Yole Developpement’s Amandine Pizzagalli has just issued a report "Glass Substrates for Semiconductor manufacturing," where she has examined the potential applications for glass in wafer level packaging and reported on the current and projected market size. A sample of the report can be found here [link]. The functions that were examined include: carriers for thinning in 2.5/3D; capping layers for CMOS image sensors, wafer level optics, structural substrates and wafer level capping.

A grid of application vs function would look something like this.


The market breakdown by end application is shown below with MEMs and image sensing being responsible for over 50 percent of the market for more than the next five years..

Total market glass market is reported to be  $158M in 2012. Schott (Germany) , Tecnisco (Japan), PlanOptik (Germany), Bullen(USA) and Corning (USA) reportedly share 70 percent of the market, driven mainly by demand for WL capping [CIS application (see below)].

CS wafer level glass capping is shown below .



For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.



IFTLE 143 HMC status; Pkging Materials $$ now Exceed Wafer Fab Materials

Hybrid Memory Cube Consortium

Twenty-five years after Ronald Regan made his famous demand in Berlin "Tear down this wall," Micron, Samsung and early hybrid memory cube consortium members promised to tear down the memory wall [ see IFTLE 38, "IFTLE 38 of Memory Cubes and IvyBridges - more 3D and TSV"], which was viewed as holding up the progress of future microelectronic products.

Since recent IFTLE reports have indicated that delays in 2.5/3D commercialization have been due to a lack of TSV memory stacks (or at least TSV memory stacks at the right cost point) [see IFTLE 140 "Important Apple Rumors; Xilinx not Deserting 2.5D;Book to Bill Improving"], we thought it was appropriate to take a look at the current status of HMC. Updates on their progress can be found here [link].

ARM, HP, and SK Hynix joined former members including Micron, Samsung, Altera, IBM, Microsoft, AMD, Fujitsu, ST Micro, Marvell and Xilinx in June 2012.

The Hybrid memory Cube [link]
 The group has recently issued version 1.0 of its specification for a vertical memory stack with a defined logic-layer interface. The group is reportedly changing focus to higher-speed variations of a DRAM stacked using TSV technology. They want to increase data rate across modules from the current 10 – 15 Gb/sec up to 28 Gb/sec.

Micron said it will deliver engineering samples of 2 and 4 Gb versions of the stack by this summer with commercial production scheduled for late 2013 or early 2014.
 High-speed networking vendors will probably be the first to commercialize with  HPC-centric applications next in line. Initial HMC implementations will be DRAM, but multi-memory stacks that employ NAND flash and DRAM are expected to follow.[link].
  
2012 Semiconductor Revenue
Gartner reports that total worldwide semiconductor revenue was $299.9B in 2012, down 2.6 percent. The top 25  vendors accounted for almost the same portion of the industry’s total revenue as compared to 2011.
Intel retained its number one position despite a 3.1 percent revenue decline  (due to decline in PC shipments).  Number two Samsung saw weak DRAM growth although its overall revenue increased from smartphone ASICs and application-specific standard products. Qualcomm, which climbed to number three, continues to benefit from its leading position in wireless semiconductors. Texas Instruments retained its fourth-place ranking, although Toshiba slipped to fifth place in semiconductor shipments.

2012 Top 10 Semiconductor Vendors

2012 Materials Market

Semi just reported that the global semiconductor materials market decreased 2 percent in 2012 to $47.11B the first decline in three years. Packaging materials exceeded wafer fabrication materials for the first time ever $23.74B vs $23.38B.

For the third year in a row, Taiwan is the largest consumer of semiconductor materials due to its large foundry and advanced packaging base. Materials markets in China and South Korea also experienced increases. The materials market in Japan contracted 7 percent, with markets also contracting in Europe and North America.


   2011-2012 Semiconductor Materials Market by World Region

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